lcdfinal.tan.rpt

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; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLOCK_50        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLOCK_50'                                                                                                                                                                                                                                                                     ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------+-----------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                  ; To                                      ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------+-----------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 252.53 MHz ( period = 3.960 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[7]        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.744 ns                ;
; N/A                                     ; 252.53 MHz ( period = 3.960 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[5]        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.744 ns                ;
; N/A                                     ; 252.53 MHz ( period = 3.960 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[6]        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.744 ns                ;
; N/A                                     ; 252.53 MHz ( period = 3.960 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[8]        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.744 ns                ;
; N/A                                     ; 252.53 MHz ( period = 3.960 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[1]        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.744 ns                ;
; N/A                                     ; 252.53 MHz ( period = 3.960 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[4]        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.744 ns                ;
; N/A                                     ; 252.53 MHz ( period = 3.960 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[3]        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.744 ns                ;
; N/A                                     ; 252.53 MHz ( period = 3.960 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[2]        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.744 ns                ;
; N/A                                     ; 252.53 MHz ( period = 3.960 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[0]        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.744 ns                ;
; N/A                                     ; 256.87 MHz ( period = 3.893 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[17]       ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.679 ns                ;
; N/A                                     ; 256.87 MHz ( period = 3.893 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[15]       ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.679 ns                ;
; N/A                                     ; 256.87 MHz ( period = 3.893 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[16]       ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.679 ns                ;
; N/A                                     ; 256.87 MHz ( period = 3.893 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[13]       ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.679 ns                ;
; N/A                                     ; 256.87 MHz ( period = 3.893 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[14]       ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.679 ns                ;
; N/A                                     ; 256.87 MHz ( period = 3.893 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[12]       ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.679 ns                ;
; N/A                                     ; 256.87 MHz ( period = 3.893 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[11]       ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.679 ns                ;
; N/A                                     ; 256.87 MHz ( period = 3.893 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[10]       ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.679 ns                ;
; N/A                                     ; 256.87 MHz ( period = 3.893 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[9]      ; LCD_TEST_systemlocked:u3|mDLY[9]        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.679 ns                ;
; N/A                                     ; 265.11 MHz ( period = 3.772 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[5]      ; LCD_TEST_systemlocked:u3|mDLY[7]        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.558 ns                ;
; N/A                                     ; 265.11 MHz ( period = 3.772 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[5]      ; LCD_TEST_systemlocked:u3|mDLY[5]        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.558 ns                ;
; N/A                                     ; 265.11 MHz ( period = 3.772 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[5]      ; LCD_TEST_systemlocked:u3|mDLY[6]        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.558 ns                ;
; N/A                                     ; 265.11 MHz ( period = 3.772 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[5]      ; LCD_TEST_systemlocked:u3|mDLY[8]        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.558 ns                ;
; N/A                                     ; 265.11 MHz ( period = 3.772 ns )                    ; LCD_TEST_systemlocked:u3|mDLY[5]      ; LCD_TEST_systemlocked:u3|mDLY[1]        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.558 ns                ;