ccd_dr.tan.rpt

verilog HDL语言

; N/A   ; None         ; 3.100 ns   ; cnt2[11]~reg0 ; cnt2[11] ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt2[10]~reg0 ; cnt2[10] ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt2[9]~reg0  ; cnt2[9]  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt2[8]~reg0  ; cnt2[8]  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt2[7]~reg0  ; cnt2[7]  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt2[6]~reg0  ; cnt2[6]  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt2[5]~reg0  ; cnt2[5]  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt2[4]~reg0  ; cnt2[4]  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt2[3]~reg0  ; cnt2[3]  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt2[1]~reg0  ; cnt2[1]  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; ccd_clk~reg0  ; ccd_clk  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt1[1]~reg0  ; cnt1[1]  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt2[0]~reg0  ; cnt2[0]  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt1[7]~reg0  ; cnt1[7]  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt1[6]~reg0  ; cnt1[6]  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt1[5]~reg0  ; cnt1[5]  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt1[4]~reg0  ; cnt1[4]  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt1[3]~reg0  ; cnt1[3]  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt1[2]~reg0  ; cnt1[2]  ; clk        ;
; N/A   ; None         ; 3.100 ns   ; cnt1[0]~reg0  ; cnt1[0]  ; clk        ;
+-------+--------------+------------+---------------+----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Jul 01 21:23:53 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CCD_DRIVER -c ccd_dr
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 151.52 MHz between source register "cnt1[5]~reg0" and destination register "ccd_sh~reg0" (period= 6.6 ns)
    Info: + Longest register to register delay is 4.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 33; REG Node = 'cnt1[5]~reg0'
        Info: 2: + IC(1.300 ns) + CELL(1.800 ns) = 3.100 ns; Loc. = SEXP38; Fanout = 1; COMB Node = 'Selector4~111'
        Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 4.600 ns; Loc. = LC36; Fanout = 4; REG Node = 'ccd_sh~reg0'
        Info: Total cell delay = 3.300 ns ( 71.74 % )
        Info: Total interconnect delay = 1.300 ns ( 28.26 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 1.600 ns
            Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_43; Fanout = 27; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.600 ns; Loc. = LC36; Fanout = 4; REG Node = 'ccd_sh~reg0'
            Info: Total cell delay = 1.600 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 1.600 ns
            Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_43; Fanout = 27; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.600 ns; Loc. = LC3; Fanout = 33; REG Node = 'cnt1[5]~reg0'
            Info: Total cell delay = 1.600 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Micro setup delay of destination is 1.300 ns
Info: tco from clock "clk" to destination pin "ccd_cp" through register "ccd_sh~reg0" is 6.300 ns
    Info: + Longest clock path from clock "clk" to source register is 1.600 ns
        Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_43; Fanout = 27; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.600 ns; Loc. = LC36; Fanout = 4; REG Node = 'ccd_sh~reg0'
        Info: Total cell delay = 1.600 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Longest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC36; Fanout = 4; REG Node = 'ccd_sh~reg0'
        Info: 2: + IC(1.100 ns) + CELL(2.100 ns) = 3.200 ns; Loc. = LC17; Fanout = 1; COMB Node = 'ccd_cp~9'
        Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 4.000 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'ccd_cp'
        Info: Total cell delay = 2.900 ns ( 72.50 % )
        Info: Total interconnect delay = 1.100 ns ( 27.50 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 109 megabytes of memory during processing
    Info: Processing ended: Tue Jul 01 21:23:56 2008
    Info: Elapsed time: 00:00:03