ccd_dr.fit.summary

来自「verilog HDL语言」· SUMMARY 代码 · 共 10 行

Fitter Status : Successful - Tue Jul 01 21:23:32 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : ccd_dr
Top-level Entity Name : ccd_dr
Family : MAX7000AE
Device : EPM7064AELC44-4
Timing Models : Final
Total macrocells : 30 / 64 ( 47 % )
Total pins : 32 / 36 ( 89 % )