adder.vhd

用VHDL语言实现通用计算器设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity adder is
port(a: in std_logic;
b:in std_logic;
ci:in std_logic;
s: out std_logic;
co:out std_logic
);
end adder;

architecture rt1 of adder is

signal tem: std_logic;
signal stem: std_logic;

begin
tem<=a xor b;
stem<=tem xor ci;
co<=(tem and ci) or (a and b);
s<=stem;
end rt1;