📄 cal.rpt
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C9 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
C10 6/ 8( 75%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 15/22( 68%)
C11 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 9/22( 40%)
C12 5/ 8( 62%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 12/22( 54%)
C13 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 6/22( 27%)
C14 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
C15 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
C16 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 4/22( 18%)
C17 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
C18 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
C19 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 2/2 2/2 11/22( 50%)
C20 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 10/22( 45%)
C21 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 2/2 15/22( 68%)
C22 6/ 8( 75%) 2/ 8( 25%) 0/ 8( 0%) 1/2 1/2 9/22( 40%)
C23 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 1/2 1/2 14/22( 63%)
C24 7/ 8( 87%) 2/ 8( 25%) 0/ 8( 0%) 1/2 1/2 13/22( 59%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 32/53 ( 60%)
Total logic cells used: 473/576 ( 82%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.45/4 ( 86%)
Total fan-in: 1636/2304 ( 71%)
Total input pins required: 17
Total input I/O cell registers required: 0
Total output pins required: 21
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 473
Total flipflops required: 97
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 107/ 576 ( 18%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 5 8 6 5 4 7 8 7 4 8 7 0 8 8 5 7 5 8 7 4 7 4 8 5 153/0
B: 7 8 8 6 6 6 4 6 3 6 8 8 0 8 7 7 7 6 7 7 6 7 8 8 6 160/0
C: 8 8 6 8 7 8 6 6 7 6 7 5 0 3 6 6 3 8 8 7 8 8 6 8 7 160/0
Total: 23 21 22 20 18 18 17 20 17 16 23 20 0 19 21 18 17 19 23 21 18 22 18 24 18 473/0
Device-Specific Information: c:\work\cal.rpt
cal
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
42 - - - -- INPUT G 0 0 0 2 c
43 - - - -- INPUT G 0 0 0 0 clk
1 - - - -- INPUT G 0 0 0 1 equal
44 - - - -- INPUT 0 0 0 3 mdiv
2 - - - -- INPUT 0 0 0 4 mult
73 - - A -- INPUT 0 0 0 5 num0
70 - - A -- INPUT 0 0 0 5 num1
11 - - - 01 INPUT 0 0 0 5 num2
16 - - A -- INPUT 0 0 0 4 num3
17 - - A -- INPUT 0 0 0 4 num4
19 - - A -- INPUT 0 0 0 4 num5
84 - - - -- INPUT 0 0 0 4 num6
18 - - A -- INPUT 0 0 0 5 num7
7 - - - 03 INPUT 0 0 0 3 num8
8 - - - 03 INPUT 0 0 0 5 num9
71 - - A -- INPUT 0 0 0 3 plus
10 - - - 01 INPUT 0 0 0 3 subt
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\work\cal.rpt
cal
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
29 - - C -- OUTPUT 0 1 0 0 onum10
69 - - A -- OUTPUT 0 1 0 0 onum11
72 - - A -- OUTPUT 0 1 0 0 onum12
23 - - B -- OUTPUT 0 1 0 0 onum13
61 - - C -- OUTPUT 0 1 0 0 onum14
47 - - - 14 OUTPUT 0 1 0 0 onum15
64 - - B -- OUTPUT 0 1 0 0 onum16
53 - - - 20 OUTPUT 0 1 0 0 onum20
48 - - - 15 OUTPUT 0 1 0 0 onum21
49 - - - 16 OUTPUT 0 1 0 0 onum22
58 - - C -- OUTPUT 0 1 0 0 onum23
59 - - C -- OUTPUT 0 1 0 0 onum24
50 - - - 17 OUTPUT 0 1 0 0 onum25
54 - - - 21 OUTPUT 0 1 0 0 onum26
83 - - - 13 OUTPUT 0 1 0 0 onum30
65 - - B -- OUTPUT 0 1 0 0 onum31
22 - - B -- OUTPUT 0 1 0 0 onum32
30 - - C -- OUTPUT 0 1 0 0 onum33
24 - - B -- OUTPUT 0 1 0 0 onum34
25 - - B -- OUTPUT 0 1 0 0 onum35
60 - - C -- OUTPUT 0 1 0 0 onum36
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\work\cal.rpt
cal
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - A 05 SOFT s ! 1 0 0 9 c~1
- 1 - B 04 OR2 0 4 0 1 |div:d1|sub4:u1|adder:add~62|:11
- 5 - B 04 OR2 0 4 0 2 |div:d1|sub4:u1|adder:add~62|:14
- 1 - B 03 OR2 0 3 0 1 |div:d1|sub4:u1|adder:add~93|:14
- 4 - B 03 OR2 0 3 0 15 |div:d1|sub4:u1|adder:add~116|:14
- 5 - B 16 DFFE + 0 2 0 1 |div:d1|:15
- 1 - B 16 DFFE + 0 2 0 1 |div:d1|:17
- 6 - B 16 DFFE + 0 2 0 1 |div:d1|:19
- 2 - B 16 DFFE + 0 2 0 1 |div:d1|:21
- 3 - B 16 DFFE + 0 2 0 4 |div:d1|state2 (|div:d1|:31)
- 8 - B 13 DFFE + 0 4 0 4 |div:d1|state1 (|div:d1|:32)
- 7 - B 13 DFFE + 0 4 0 4 |div:d1|state0 (|div:d1|:33)
- 4 - B 05 DFFE + 0 4 0 3 |div:d1|atem3 (|div:d1|:34)
- 3 - B 03 DFFE + 0 4 0 4 |div:d1|atem2 (|div:d1|:35)
- 3 - B 06 DFFE + 0 4 0 5 |div:d1|atem1 (|div:d1|:36)
- 7 - B 10 DFFE + 0 4 0 5 |div:d1|atem0 (|div:d1|:37)
- 5 - B 03 DFFE + 0 3 0 1 |div:d1|btem3 (|div:d1|:38)
- 6 - B 03 DFFE + 0 3 0 2 |div:d1|btem2 (|div:d1|:39)
- 2 - B 04 DFFE + 0 3 0 2 |div:d1|btem1 (|div:d1|:40)
- 4 - B 04 DFFE + 0 3 0 3 |div:d1|btem0 (|div:d1|:41)
- 2 - B 06 DFFE + 0 3 0 1 |div:d1|ain6 (|div:d1|:43)
- 8 - B 07 DFFE + 0 3 0 1 |div:d1|ain5 (|div:d1|:44)
- 4 - B 06 DFFE + 0 3 0 1 |div:d1|ain4 (|div:d1|:45)
- 4 - B 02 DFFE + 0 4 0 4 |div:d1|ain3 (|div:d1|:46)
- 5 - B 02 DFFE + 0 4 0 6 |div:d1|ain2 (|div:d1|:47)
- 1 - B 01 DFFE + 0 4 0 6 |div:d1|ain1 (|div:d1|:48)
- 3 - B 01 DFFE + 0 3 0 5 |div:d1|ain0 (|div:d1|:49)
- 3 - B 13 DFFE + 0 3 0 2 |div:d1|n1 (|div:d1|:60)
- 5 - B 13 DFFE + 0 3 0 2 |div:d1|n0 (|div:d1|:61)
- 6 - B 05 OR2 0 3 0 1 |div:d1|:431
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