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📄 cal.rpt

📁 用VHDL语言实现通用计算器设计
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|lpm_add_sub:3731|altshift:result_ext_latency_ffs|
|lpm_add_sub:3731|altshift:carry_ext_latency_ffs|
|lpm_add_sub:3731|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:3780|
|lpm_add_sub:3780|addcore:adder|
|lpm_add_sub:3780|altshift:result_ext_latency_ffs|
|lpm_add_sub:3780|altshift:carry_ext_latency_ffs|
|lpm_add_sub:3780|altshift:oflow_ext_latency_ffs|
|numdecoder:inum1|
|div:d1|
|div:d1|lpm_add_sub:924|
|div:d1|lpm_add_sub:924|addcore:adder|
|div:d1|lpm_add_sub:924|altshift:result_ext_latency_ffs|
|div:d1|lpm_add_sub:924|altshift:carry_ext_latency_ffs|
|div:d1|lpm_add_sub:924|altshift:oflow_ext_latency_ffs|
|div:d1|sub4:u1|
|div:d1|sub4:u1|adder:add|
|div:d1|sub4:u1|adder:add~62|
|div:d1|sub4:u1|adder:add~93|
|div:d1|sub4:u1|adder:add~116|
|vdecode:v1|
|vdecode:v2|
|vdecode:v3|


Device-Specific Information:                                   c:\work\cal.rpt
cal

***** Logic for device 'cal' compiled without errors.




Device: EPF10K10LC84-4

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f



Device-Specific Information:                                   c:\work\cal.rpt
cal

** ERROR SUMMARY **

Info: Chip 'cal' in device 'EPF10K10LC84-4' has less than 20% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                                                                         ^     
                                                                         C     
                      R        R  R     R                 R  R  R  R     O     
                      E        E  E     E                 E  E  E  E     N     
                      S        S  S  V  S           o  G  S  S  S  S     F     
                      E        E  E  C  E     e     n  N  E  E  E  E     _  ^  
                n  s  R  n  n  R  R  C  R  m  q  n  u  D  R  R  R  R  #  D  n  
                u  u  V  u  u  V  V  I  V  u  u  u  m  I  V  V  V  V  T  O  C  
                m  b  E  m  m  E  E  N  E  l  a  m  3  N  E  E  E  E  C  N  E  
                2  t  D  9  8  D  D  T  D  t  l  6  0  T  D  D  D  D  K  E  O  
              -----------------------------------------------------------------_ 
            /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
    ^DATA0 | 12                                                              74 | #TDO 
     ^DCLK | 13                                                              73 | num0 
      ^nCE | 14                                                              72 | onum12 
      #TDI | 15                                                              71 | plus 
      num3 | 16                                                              70 | num1 
      num4 | 17                                                              69 | onum11 
      num7 | 18                                                              68 | GNDINT 
      num5 | 19                                                              67 | RESERVED 
    VCCINT | 20                                                              66 | RESERVED 
  RESERVED | 21                                                              65 | onum31 
    onum32 | 22                        EPF10K10LC84-4                        64 | onum16 
    onum13 | 23                                                              63 | VCCINT 
    onum34 | 24                                                              62 | RESERVED 
    onum35 | 25                                                              61 | onum14 
    GNDINT | 26                                                              60 | onum36 
  RESERVED | 27                                                              59 | onum24 
  RESERVED | 28                                                              58 | onum23 
    onum10 | 29                                                              57 | #TMS 
    onum33 | 30                                                              56 | #TRST 
    ^MSEL0 | 31                                                              55 | ^nSTATUS 
    ^MSEL1 | 32                                                              54 | onum26 
           |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
             ------------------------------------------------------------------ 
                V  ^  R  R  R  R  R  V  G  c  c  m  V  G  o  o  o  o  R  R  o  
                C  n  E  E  E  E  E  C  N     l  d  C  N  n  n  n  n  E  E  n  
                C  C  S  S  S  S  S  C  D     k  i  C  D  u  u  u  u  S  S  u  
                I  O  E  E  E  E  E  I  I        v  I  I  m  m  m  m  E  E  m  
                N  N  R  R  R  R  R  N  N           N  N  1  2  2  2  R  R  2  
                T  F  V  V  V  V  V  T  T           T  T  5  1  2  5  V  V  0  
                   I  E  E  E  E  E                                   E  E     
                   G  D  D  D  D  D                                   D  D     
                                                                               
                                                                               


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:                                   c:\work\cal.rpt
cal

** RESOURCE USAGE **

Logic                Column       Row                                   
Array                Interconnect Interconnect         Clears/     External  
Block   Logic Cells  Driven       Driven       Clocks  Presets   Interconnect
A1       8/ 8(100%)   3/ 8( 37%)   0/ 8(  0%)    1/2    1/2       9/22( 40%)   
A2       5/ 8( 62%)   3/ 8( 37%)   2/ 8( 25%)    2/2    2/2      13/22( 59%)   
A3       8/ 8(100%)   3/ 8( 37%)   0/ 8(  0%)    1/2    1/2       7/22( 31%)   
A4       6/ 8( 75%)   4/ 8( 50%)   1/ 8( 12%)    1/2    1/2       6/22( 27%)   
A5       5/ 8( 62%)   1/ 8( 12%)   5/ 8( 62%)    1/2    1/2       9/22( 40%)   
A6       4/ 8( 50%)   1/ 8( 12%)   4/ 8( 50%)    1/2    1/2       8/22( 36%)   
A7       7/ 8( 87%)   0/ 8(  0%)   3/ 8( 37%)    0/2    0/2       7/22( 31%)   
A8       8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    1/2    1/2       8/22( 36%)   
A9       7/ 8( 87%)   2/ 8( 25%)   3/ 8( 37%)    1/2    1/2       8/22( 36%)   
A10      4/ 8( 50%)   2/ 8( 25%)   3/ 8( 37%)    1/2    1/2       6/22( 27%)   
A11      8/ 8(100%)   1/ 8( 12%)   4/ 8( 50%)    1/2    1/2       7/22( 31%)   
A12      7/ 8( 87%)   0/ 8(  0%)   4/ 8( 50%)    0/2    0/2      11/22( 50%)   
A13      8/ 8(100%)   7/ 8( 87%)   0/ 8(  0%)    1/2    1/2       6/22( 27%)   
A14      8/ 8(100%)   5/ 8( 62%)   2/ 8( 25%)    1/2    1/2       6/22( 27%)   
A15      5/ 8( 62%)   5/ 8( 62%)   1/ 8( 12%)    1/2    1/2       5/22( 22%)   
A16      7/ 8( 87%)   0/ 8(  0%)   5/ 8( 62%)    1/2    1/2      10/22( 45%)   
A17      5/ 8( 62%)   1/ 8( 12%)   2/ 8( 25%)    1/2    1/2      10/22( 45%)   
A18      8/ 8(100%)   2/ 8( 25%)   2/ 8( 25%)    1/2    0/2      13/22( 59%)   
A19      7/ 8( 87%)   2/ 8( 25%)   4/ 8( 50%)    0/2    0/2       6/22( 27%)   
A20      4/ 8( 50%)   2/ 8( 25%)   3/ 8( 37%)    1/2    1/2       9/22( 40%)   
A21      7/ 8( 87%)   2/ 8( 25%)   3/ 8( 37%)    1/2    1/2      11/22( 50%)   
A22      4/ 8( 50%)   1/ 8( 12%)   3/ 8( 37%)    1/2    1/2       7/22( 31%)   
A23      8/ 8(100%)   1/ 8( 12%)   3/ 8( 37%)    1/2    0/2      13/22( 59%)   
A24      5/ 8( 62%)   1/ 8( 12%)   2/ 8( 25%)    1/2    1/2       6/22( 27%)   
B1       7/ 8( 87%)   0/ 8(  0%)   2/ 8( 25%)    1/2    0/2       7/22( 31%)   
B2       8/ 8(100%)   0/ 8(  0%)   2/ 8( 25%)    1/2    0/2       8/22( 36%)   
B3       8/ 8(100%)   0/ 8(  0%)   2/ 8( 25%)    1/2    0/2      12/22( 54%)   
B4       6/ 8( 75%)   0/ 8(  0%)   3/ 8( 37%)    1/2    0/2       8/22( 36%)   
B5       6/ 8( 75%)   1/ 8( 12%)   1/ 8( 12%)    1/2    0/2      12/22( 54%)   
B6       6/ 8( 75%)   0/ 8(  0%)   2/ 8( 25%)    1/2    0/2       9/22( 40%)   
B7       4/ 8( 50%)   1/ 8( 12%)   4/ 8( 50%)    1/2    1/2      11/22( 50%)   
B8       6/ 8( 75%)   2/ 8( 25%)   1/ 8( 12%)    1/2    1/2      11/22( 50%)   
B9       3/ 8( 37%)   1/ 8( 12%)   2/ 8( 25%)    0/2    0/2       7/22( 31%)   
B10      6/ 8( 75%)   0/ 8(  0%)   2/ 8( 25%)    2/2    1/2      12/22( 54%)   
B11      8/ 8(100%)   2/ 8( 25%)   2/ 8( 25%)    0/2    0/2      14/22( 63%)   
B12      8/ 8(100%)   1/ 8( 12%)   2/ 8( 25%)    1/2    1/2      14/22( 63%)   
B13      8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    1/2    0/2       4/22( 18%)   
B14      7/ 8( 87%)   0/ 8(  0%)   2/ 8( 25%)    0/2    0/2      11/22( 50%)   
B15      7/ 8( 87%)   0/ 8(  0%)   6/ 8( 75%)    0/2    0/2       5/22( 22%)   
B16      7/ 8( 87%)   4/ 8( 50%)   3/ 8( 37%)    1/2    0/2      10/22( 45%)   
B17      6/ 8( 75%)   3/ 8( 37%)   0/ 8(  0%)    0/2    0/2       8/22( 36%)   
B18      7/ 8( 87%)   2/ 8( 25%)   5/ 8( 62%)    1/2    1/2       9/22( 40%)   
B19      7/ 8( 87%)   1/ 8( 12%)   0/ 8(  0%)    0/2    0/2      13/22( 59%)   
B20      6/ 8( 75%)   1/ 8( 12%)   1/ 8( 12%)    0/2    0/2      11/22( 50%)   
B21      7/ 8( 87%)   1/ 8( 12%)   2/ 8( 25%)    0/2    0/2      10/22( 45%)   
B22      8/ 8(100%)   1/ 8( 12%)   0/ 8(  0%)    0/2    0/2      12/22( 54%)   
B23      8/ 8(100%)   2/ 8( 25%)   1/ 8( 12%)    0/2    0/2      14/22( 63%)   
B24      6/ 8( 75%)   2/ 8( 25%)   1/ 8( 12%)    0/2    0/2      11/22( 50%)   
C1       8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    1/2    1/2      15/22( 68%)   
C2       8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    1/2    1/2      14/22( 63%)   
C3       6/ 8( 75%)   0/ 8(  0%)   5/ 8( 62%)    0/2    0/2       7/22( 31%)   
C4       8/ 8(100%)   0/ 8(  0%)   2/ 8( 25%)    1/2    1/2      14/22( 63%)   
C5       7/ 8( 87%)   0/ 8(  0%)   1/ 8( 12%)    1/2    1/2      14/22( 63%)   
C6       8/ 8(100%)   1/ 8( 12%)   1/ 8( 12%)    1/2    1/2      12/22( 54%)   
C7       6/ 8( 75%)   1/ 8( 12%)   2/ 8( 25%)    1/2    1/2      13/22( 59%)   
C8       6/ 8( 75%)   1/ 8( 12%)   2/ 8( 25%)    0/2    0/2      12/22( 54%)   

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