fpdiv.rpt

用VHDL语言实现通用计算器设计

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                                 c:\work\fpdiv.rpt
fpdiv

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:       4/ 96(  4%)     6/ 48( 12%)     0/ 48(  0%)    2/16( 12%)      5/16( 31%)     0/16(  0%)
C:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                                 c:\work\fpdiv.rpt
fpdiv

** EQUATIONS **

A0       : INPUT;
A1       : INPUT;
A2       : INPUT;
A3       : INPUT;
B0       : INPUT;
B1       : INPUT;
B2       : INPUT;
B3       : INPUT;

-- Node name is 'data_out0' 
-- Equation name is 'data_out0', type is output 
data_out0 =  _LC4_B10;

-- Node name is 'data_out1' 
-- Equation name is 'data_out1', type is output 
data_out1 =  _LC2_B8;

-- Node name is 'data_out2' 
-- Equation name is 'data_out2', type is output 
data_out2 =  _LC6_B8;

-- Node name is 'data_out3' 
-- Equation name is 'data_out3', type is output 
data_out3 =  _LC1_B8;

-- Node name is 'DIVz' 
-- Equation name is 'DIVz', type is output 
DIVz     =  _LC8_B8;

-- Node name is '|LPM_ADD_SUB:335|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_B10', type is buried 
!_LC1_B10 = _LC1_B10~NOT;
_LC1_B10~NOT = LCELL( _EQ001);
  _EQ001 = !A1 &  B0;

-- Node name is ':184' 
-- Equation name is '_LC7_B10', type is buried 
!_LC7_B10 = _LC7_B10~NOT;
_LC7_B10~NOT = LCELL( _EQ002);
  _EQ002 = !B2 &  _LC2_B10
         #  _LC2_B10 & !_LC5_B10
         # !B2 & !_LC5_B10;

-- Node name is ':189' 
-- Equation name is '_LC5_B10', type is buried 
!_LC5_B10 = _LC5_B10~NOT;
_LC5_B10~NOT = LCELL( _EQ003);
  _EQ003 = !B1 &  _LC3_B10
         # !B0 &  _LC3_B10
         # !B0 & !B1
         #  A0 &  _LC3_B10
         #  A0 & !B1;

-- Node name is ':289' 
-- Equation name is '_LC3_B8', type is buried 
!_LC3_B8 = _LC3_B8~NOT;
_LC3_B8~NOT = LCELL( _EQ004);
  _EQ004 = !B2 & !_LC4_B8 & !_LC5_B8
         # !B2 &  _LC1_B10 & !_LC5_B8;

-- Node name is ':295' 
-- Equation name is '_LC5_B8', type is buried 
!_LC5_B8 = _LC5_B8~NOT;
_LC5_B8~NOT = LCELL( _EQ005);
  _EQ005 = !B1
         #  A2;

-- Node name is ':298' 
-- Equation name is '_LC4_B8', type is buried 
!_LC4_B8 = _LC4_B8~NOT;
_LC4_B8~NOT = LCELL( _EQ006);
  _EQ006 = !B1 &  _LC6_B10
         #  B1 & !_LC6_B10;

-- Node name is '~346~1' 
-- Equation name is '~346~1', location is LC8_B10, type is buried.
-- synthesized logic cell 
_LC8_B10 = LCELL( _EQ007);
  _EQ007 = !A2 &  B1
         # !_LC1_B10 & !_LC6_B10
         #  B1 & !_LC1_B10;

-- Node name is ':363' 
-- Equation name is '_LC2_B10', type is buried 
_LC2_B10 = LCELL( _EQ008);
  _EQ008 =  B1 & !_LC1_B10 &  _LC6_B10
         # !B1 & !_LC1_B10 & !_LC3_B8 & !_LC6_B10
         # !B1 &  _LC1_B10 &  _LC6_B10
         #  B1 &  _LC1_B10 & !_LC3_B8 & !_LC6_B10
         #  _LC3_B8 &  _LC6_B10;

-- Node name is ':369' 
-- Equation name is '_LC3_B10', type is buried 
_LC3_B10 = LCELL( _EQ009);
  _EQ009 = !A1 &  B0 & !_LC3_B8
         #  A1 & !B0
         #  A1 &  _LC3_B8;

-- Node name is ':473' 
-- Equation name is '_LC6_B10', type is buried 
!_LC6_B10 = _LC6_B10~NOT;
_LC6_B10~NOT = LCELL( _EQ010);
  _EQ010 = !A2
         #  B0 & !B1 & !B2;

-- Node name is ':499' 
-- Equation name is '_LC1_B8', type is buried 
_LC1_B8  = LCELL( _EQ011);
  _EQ011 =  A3 & !B3 & !_LC8_B8
         # !A3 &  B3 & !_LC8_B8;

-- Node name is ':505' 
-- Equation name is '_LC6_B8', type is buried 
_LC6_B8  = LCELL( _EQ012);
  _EQ012 =  A2 &  B0 & !B1 & !B2;

-- Node name is ':511' 
-- Equation name is '_LC2_B8', type is buried 
_LC2_B8  = LCELL( _EQ013);
  _EQ013 = !_LC3_B8 & !_LC8_B8;

-- Node name is ':517' 
-- Equation name is '_LC4_B10', type is buried 
_LC4_B10 = LCELL( _EQ014);
  _EQ014 = !_LC7_B10 & !_LC8_B8
         # !_LC3_B8 & !_LC8_B8 &  _LC8_B10;

-- Node name is ':544' 
-- Equation name is '_LC8_B8', type is buried 
_LC8_B8  = LCELL( _EQ015);
  _EQ015 = !B0 & !B1 & !B2;



Project Information                                          c:\work\fpdiv.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 10,012K