adc0809.txt

用FPGA实现的ADC采样器,用vhdl编写

♂Denzel≯:基于FPGA的ADC0809采样 - 新浪BLOG  管理博客 ┆ 搜索 ┆ 帮助 

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作者：♂Denzel≯ 2006-11-12 00:15:33 
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当时参加电子设计大赛前训练时做的小东西，发出来分享下
由FPGA芯片EP1K30TC144-3和ADC0809及VHDL语言实现的AD转换：
主体设计图如下：

如上图本AD转换主要由分频器和ADC0809模块实现
ADC0809模块程序如下：
  LIBRARY IEEE;
  USE IEEE.STD_LOGIC_1164.ALL;
  
ENTITY ADC0809 IS
  PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
  CLK,EOC : IN STD_LOGIC;
  LOCK1,ALE,START,OE,A0,A1,A2 : OUT STD_LOGIC;
  QOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
  END ADC0809;

  ARCHITECTURE behav OF ADC0809 IS
  TYPE states IS (st0,st1,st2,st3,st4);
  SIGNAL current_state , next_state: states :=st0 ;
  SIGNAL REGL : STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL LOCK : STD_LOGIC;
  BEGIN
  A0 <= '0';A1 <='0';A2<='0'; LOCK1 <=LOCK; QOUT<=REGL;
  COM1: PROCESS(current_state,EOC)
  BEGIN
  CASE current_state IS
  WHEN st0 => next_state <= st1;
  WHEN st1 => next_state <= st2;
  WHEN st2 => IF (EOC='1') THEN next_state <= st3;
  ELSE next_state <= st2;
  END IF;
  WHEN st3 => next_state <= st4;
  WHEN st4 => next_state <= st0;
  WHEN OTHERS => next_state <= st0;
  END CASE ;
  END PROCESS COM1 ;

  COM2: PROCESS(current_state)
  BEGIN
  CASE current_state IS
  WHEN st0 => ALE<='0';START<='0';OE<='0';LOCK<='0';
  WHEN st1 => ALE<='1';START<='1';OE<='0';LOCK<='0';
  WHEN st2 => ALE<='0';START<='0';OE<='0';LOCK<='0';
  WHEN st3 => ALE<='0';START<='0';OE<='1';LOCK<='0';
  WHEN st4 => ALE<='0';START<='0';OE<='1';LOCK<='1';
  WHEN OTHERS => ALE<='0';START<='0';LOCK<='0';
  END CASE;
  END PROCESS COM2;

  PROCESS (CLK)
  BEGIN
  IF (CLK'EVENT AND CLK='1') THEN
  current_state <= next_state;
  END IF;
  END PROCESS;
  PROCESS (LOCK)
  BEGIN
  IF LOCK='1' AND LOCK'EVENT THEN REGL <=D;
  END IF;
  END PROCESS;
  END behav
软件分频器模块程序如下：
  LIBRARY IEEE;
  USE IEEE.STD_LOGIC_1164.ALL;
  USE IEEE.STD_LOGIC_ARITH.ALL;
  USE IEEE.STD_LOGIC_UNSIGNED.ALL;
  ?/P>
  ENTITY clkdiv8 IS
  PORT( clk : IN STD_LOGIC;
  clk_div8 : OUT STD_LOGIC);
  END clkdiv8;
  ARCHITECTURE one OF clkdiv8 IS
  SIGNAL count : STD_LOGIC_VECTOR(6 DOWNTO 0);
  BEGIN
  PROCESS(clk)
  BEGIN
  IF (clk'event AND clk='1' ) THEN
  IF(count= "1111111" ) THEN
  count <= (OTHERS =>'0' );
  ELSE
  count <= count +1;
  END IF ;
  END IF ;
  END PROCESS;
  clk_div8 <= count(6);
  END one;
仿真图如下：

以上设计我已用硬件实现过，在秒向分进位和分向时进位及23时置0时有毛刺，分别会显示“60秒”1秒钟，“60分”1秒钟，“24时”1秒钟。
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