display.vhd

实现嵌入式系统的秒表计时

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity display is
port(
     clk_1K:in std_logic;
     csl : in integer range 0 to 9; 
     csh : in integer range 0 to 5;
     cml : in integer range 0 to 9;
     cmh : in integer range 0 to 5; 
     chl : in integer range 0 to 9;  
     chh : in integer range 0 to 2;
        bell_h1: in integer range 0 to 9;
         bell_h2: in integer range 0 to 2;
         bell_m1: in integer range 0 to 9;
         bell_m2: in integer range 0 to 5;
         bell_s1: in integer range 0 to 9;
         bell_s2: in integer range 0 to 5;
         bell_en: in  std_logic; 
     sel_1:out std_logic_vector(5 downto 0);
     seg_show:out std_logic_vector(6 downto 0)
);
end display;

architecture display_arch of display is
signal count:integer range 0 to 9;
begin

p1:process(clk_1K)
variable circle : std_logic_vector(2 downto 0);
begin
if(clk_1K'event and clk_1K='1')then
  if(circle="000")then
if(bell_en='0')then
      count<=csl;
else
    count<=bell_s1;
end if;
    sel_1<="111110";
    circle:=circle+1;

  elsif(circle="001")then
if(bell_en='0')then
      count<=csh;
else
count<=bell_s2;
end if;
    sel_1<="111101";
    circle:=circle+1;

   elsif(circle="010")then
if(bell_en='0')then
      count<=cml;
else
 count<=bell_m1;
end if;
    sel_1<="111011";
    circle:=circle+1;

   elsif(circle="011")then
if(bell_en='0')then
      count<=cmh;
else 
count<=bell_m2;
end if;
    sel_1<="110111";
    circle:=circle+1;

   elsif(circle="100")then    
if(bell_en='0')then
 count<=chl;
else
count<=bell_h1;
end if;
 sel_1<="101111";
    circle:=circle+1;

   elsif(circle="101")then
if(bell_en='0')then
      count<=chh;
else
count<=bell_h2;
end if;
    sel_1<="011111";
    circle:="000";
end if;
end if;
end process;

p2:process(count)
begin
case count is
  when 0=>seg_show<="1111110";
  when 1=>seg_show<="0110000";
  when 2=>seg_show<="1101101";
  when 3=>seg_show<="1111001";
  when 4=>seg_show<="0110011";
  when 5=>seg_show<="1011011";
  when 6=>seg_show<="1011111";
  when 7=>seg_show<="1110000";
  when 8=>seg_show<="1111111";
  when 9=>seg_show<="1111011";
end case;
end process;
end;