📄 top.qsf
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# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any other
# associated documentation or information provided by Altera or a partner
# under Altera's Megafunction Partnership Program may be used only
# to program PLD devices (but not masked PLD devices) from Altera. Any
# other use of such megafunction design, netlist, support information,
# device programming or simulation file, or any other related documentation
# or information is prohibited for any other purpose, including, but not
# limited to modification, reverse engineering, de-compiling, or use with
# any other silicon devices, unless such use is explicitly licensed under
# a separate agreement with Altera or a megafunction partner. Title to the
# intellectual property, including patents, copyrights, trademarks, trade
# secrets, or maskworks, embodied in any such megafunction design, netlist,
# support information, device programming or simulation file, or any other
# related documentation or information provided by Altera or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.
# The default values for assignments are stored in the file
# top_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:30:39 OCTOBER 27, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 4.1
set_global_assignment -name VHDL_FILE all_count.vhd
set_global_assignment -name VHDL_FILE display.vhd
set_global_assignment -name VHDL_FILE input.vhd
set_global_assignment -name VHDL_FILE minute.vhd
set_global_assignment -name VHDL_FILE second.vhd
set_global_assignment -name VHDL_FILE top.vhd
set_global_assignment -name VHDL_FILE hour.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE top.vwf
set_global_assignment -name VHDL_FILE bell.vhd
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_25 -to am_pm
set_location_assignment PIN_2 -to bell_key
set_location_assignment PIN_83 -to clk_1M
set_location_assignment PIN_84 -to fun_key
set_location_assignment PIN_1 -to set_key
set_location_assignment PIN_8 -to sound_out
set_location_assignment PIN_17 -to seg_show\[0\]
set_location_assignment PIN_16 -to seg_show\[1\]
set_location_assignment PIN_15 -to seg_show\[2\]
set_location_assignment PIN_12 -to seg_show\[3\]
set_location_assignment PIN_11 -to seg_show\[4\]
set_location_assignment PIN_10 -to seg_show\[5\]
set_location_assignment PIN_9 -to seg_show\[6\]
set_location_assignment PIN_41 -to sel_1\[0\]
set_location_assignment PIN_40 -to sel_1\[1\]
set_location_assignment PIN_39 -to sel_1\[2\]
set_location_assignment PIN_37 -to sel_1\[3\]
set_location_assignment PIN_36 -to sel_1\[4\]
set_location_assignment PIN_35 -to sel_1\[5\]
set_location_assignment PIN_4 -to over_key
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name TOP_LEVEL_ENTITY top
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EPM7128SLC84-15"
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