top.map.rpt

实现嵌入式系统的秒表计时

; |top                            ; 127        ; 20   ; |top                                             ;
;    |all_count:u2|               ; 46         ; 0    ; |top|all_count:u2                                ;
;       |hour:u3|                 ; 11         ; 0    ; |top|all_count:u2|hour:u3                        ;
;          |lpm_counter:hl_rtl_0| ; 7          ; 0    ; |top|all_count:u2|hour:u3|lpm_counter:hl_rtl_0   ;
;       |minute:u2|               ; 10         ; 0    ; |top|all_count:u2|minute:u2                      ;
;          |lpm_counter:ml_rtl_3| ; 6          ; 0    ; |top|all_count:u2|minute:u2|lpm_counter:ml_rtl_3 ;
;       |second:u1|               ; 8          ; 0    ; |top|all_count:u2|second:u1                      ;
;          |lpm_counter:sl_rtl_5| ; 4          ; 0    ; |top|all_count:u2|second:u1|lpm_counter:sl_rtl_5 ;
;    |bell:u5|                    ; 24         ; 0    ; |top|bell:u5                                     ;
;       |hour:u3|                 ; 6          ; 0    ; |top|bell:u5|hour:u3                             ;
;          |lpm_counter:hl_rtl_1| ; 4          ; 0    ; |top|bell:u5|hour:u3|lpm_counter:hl_rtl_1        ;
;       |minute:u2|               ; 7          ; 0    ; |top|bell:u5|minute:u2                           ;
;          |lpm_counter:ml_rtl_2| ; 4          ; 0    ; |top|bell:u5|minute:u2|lpm_counter:ml_rtl_2      ;
;       |second:u1|               ; 7          ; 0    ; |top|bell:u5|second:u1                           ;
;          |lpm_counter:sl_rtl_4| ; 4          ; 0    ; |top|bell:u5|second:u1|lpm_counter:sl_rtl_4      ;
;    |display:u4|                 ; 29         ; 0    ; |top|display:u4                                  ;
;    |input:u1|                   ; 26         ; 0    ; |top|input:u1                                    ;
+---------------------------------+------------+------+--------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/digital_clock/top.map.eqn.


+--------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                         ;
+--------------------------------------------------------------+-----------------+
; File Name                                                    ; Used in Netlist ;
+--------------------------------------------------------------+-----------------+
; all_count.vhd                                                ; yes             ;
; display.vhd                                                  ; yes             ;
; input.vhd                                                    ; yes             ;
; minute.vhd                                                   ; yes             ;
; second.vhd                                                   ; yes             ;
; top.vhd                                                      ; yes             ;
; hour.vhd                                                     ; yes             ;
; bell.vhd                                                     ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf  ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_constant.inc ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf  ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/addcore.inc      ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/addcore.tdf      ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf  ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/altshift.tdf     ; yes             ;
+--------------------------------------------------------------+-----------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 127                  ;
; Total registers      ; 89                   ;
; I/O pins             ; 20                   ;
; Shareable expanders  ; 18                   ;
; Parallel expanders   ; 24                   ;
; Maximum fan-out node ; input:u1|st[2]       ;
; Maximum fan-out      ; 45                   ;
; Total fan-out        ; 1028                 ;
; Average fan-out      ; 6.23                 ;
+----------------------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sun Feb 05 15:41:34 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off top -c top
Info: Found 2 design units, including 1 entities, in source file all_count.vhd
    Info: Found design unit 1: all_count-all_count_arch
    Info: Found entity 1: all_count
Info: Found 2 design units, including 1 entities, in source file display.vhd
    Info: Found design unit 1: display-display_arch
    Info: Found entity 1: display
Info: Found 2 design units, including 1 entities, in source file input.vhd
    Info: Found design unit 1: input-input_arch
    Info: Found entity 1: input
Info: Found 2 design units, including 1 entities, in source file minute.vhd
    Info: Found design unit 1: minute-minute_arch
    Info: Found entity 1: minute
Info: Found 2 design units, including 1 entities, in source file second.vhd
    Info: Found design unit 1: second-second_arch
    Info: Found entity 1: second
Info: Found 2 design units, including 1 entities, in source file top.vhd
    Info: Found design unit 1: top-behav
    Info: Found entity 1: top
Info: Found 2 design units, including 1 entities, in source file hour.vhd
    Info: Found design unit 1: hour-hour_arch
    Info: Found entity 1: hour
Info: Found 2 design units, including 1 entities, in source file bell.vhd
    Info: Found design unit 1: bell-behav
    Info: Found entity 1: bell
Warning: VHDL Process Statement warning at input.vhd(63): signal clk_1k_temp is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at input.vhd(90): signal clk_1hz_temp is in statement, but is not in sensitivity list
Info: Inferred 6 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: all_count:u2|hour:u3|hl[0]~33
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: bell:u5|hour:u3|hl[0]~33
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: bell:u5|minute:u2|ml[0]~16
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: all_count:u2|minute:u2|ml[0]~16
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: bell:u5|second:u1|sl[0]~16
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: all_count:u2|second:u1|sl[0]~16
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 7 buffer(s)
    Info: Ignored 7 SOFT buffer(s)
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin clk_1M to global clock signal
    Info: Promoted clock signal driven by pin bell_key to global clock signal
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin bell_key to global clock signal
    Info: Promoted clock signal driven by pin clk_1M to global clock signal
Info: Implemented 165 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 15 output pins
    Info: Implemented 127 macrocells
    Info: Implemented 18 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Sun Feb 05 15:42:07 2006
    Info: Elapsed time: 00:00:33