all_count.vhd

实现嵌入式系统的秒表计时

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity all_count is
port(
set:in std_logic;
ter:in std_logic;
state:in integer range 0 to 4;
clk_1HZ:in std_logic;
s_low : out integer range 0 to 9;    
s_high : out integer range 0 to 5;
m_low: out integer range 0 to 9;
m_high: out integer range 0 to 5;
h_low : out integer range 0 to 9;
h_high: out integer range 0 to 2;
bs : out std_logic;
bell_out : out std_logic;
bell_h1: in integer range 0 to 9;
bell_h2: in integer range 0 to 2;
bell_m1: in integer range 0 to 9;
bell_m2: in integer range 0 to 5;
bell_s1: in integer range 0 to 9;
bell_s2: in integer range 0 to 5);
end entity;

architecture all_count_arch of all_count is
signal s_enable:std_logic;
signal m_enable:std_logic;
signal h_enable:std_logic;
signal c1:std_logic;
signal c2:std_logic;
signal cp:std_logic;
signal sl,ml,hl:integer range 0 to 9;
signal sh,mh:integer range 0 to 5;
signal hh:integer range 0 to 2; 
signal bell_count:integer range 0 to 10;

component second is
port(clk_1HZ : in std_logic; 
 enable:in std_logic;
 s_low:out integer range 0 to 9;
 s_high:out integer range 0 to 5;
count:out std_logic); 
end component;

component minute is
port(clk_1HZ : in std_logic; 
 enable:in std_logic;
 m_low:out integer range 0 to 9;
 m_high:out integer range 0 to 5;
count:out std_logic); 
end component;

component hour is
port(clk_1HZ : in std_logic; 
 enable:in std_logic;
 h_low:out integer range 0 to 9;
 h_high:out integer range 0 to 2);
end component;

begin

p1:process(clk_1HZ,state,set,c1,c2)
begin
if(state=1)then 
s_enable<='1';
m_enable<='0';
h_enable<='0';
bs<='0';
cp<=set;
elsif(state=2)then
s_enable<='0';
m_enable<='1';
h_enable<='0';
bs<='0';
cp<=set;
elsif(state=3)then
s_enable<='0';
m_enable<='0';
h_enable<='1';
bs<='0';
cp<=set;
else 
cp<=clk_1HZ;
s_enable<='1';
m_enable<=c1;
h_enable<=c1 and c2;
bs<=c1 and c2;
end if;
end process;

u1:second port map(cp,s_enable,sl,sh,c1);
u2:minute port map(cp,m_enable,ml,mh,c2);
u3:hour port map(cp,h_enable,hl,hh);
h_low<=hl;h_high<=hh;m_low<=ml;m_high<=mh;s_low<=sl;s_high<=sh;

p2:process(hl,hh,ml,mh,sl,sh,bell_h1,bell_h2,bell_m1,bell_m2,bell_s1,bell_s2,clk_1HZ,ter)
begin
if(clk_1HZ'event and clk_1HZ='1')then
bell_count<=bell_count+1;
if(bell_count=10)then
bell_count<=10;
end if;
if(bell_h1=hl and bell_h2=hh and bell_m1=ml and bell_m2=mh and bell_s2=sh and bell_s1=sl+2)
then bell_count<=0;
end if;
if(bell_count>=0 and bell_count<10)then
  bell_out<='1';
   if(ter='1')then bell_count<=9;
   elsif(ter='0')then bell_out<='1';
    end if;
else bell_out<='0';
end if;

 end if;
end process;
end;