dffr.v

实现USB接口功能的VHDL和verilog完整源代码

/****************************************************************************
 * 
 * parts.v   - company wide parts mapping file. this is RTL for the parts
 *             we instantiate. use this file for your verilog simulations only.
 *             During synthesis, you'll point to the library specific mapped
 *             counterpart of this file - parts.vg  Actually you'll point to
 *             a directory where a .db exists for each part, 
 *             those .db(s) come from the parts.vg mapping.
 *             Put this in your files.v to scan this file during simulation:
 *             -v /projects/lib/files.v
 * 
 * Note : pad cells are mapped in padparts.v
 * 
 *   Cell naming convention:
 *   the first number if it has a leading "" will be how wide it is, 
 *   other numbers not
 *   surrounded by "" denote function (or2,mux2x2), if the name ends in
 *   x# the # is the drive strength. 
 * 
 *   mux2x1 - 2:1 mux
 *   mux322x1 32 bit wide 2:1 mux
 *   or2 - 2 bit or gate
 *   or2x4 - 2 bit or with 4x drive
 *   or28x2 - 8 bit wide 2 bit or with 2x drive
 *   invx4 - inverter with 4x drive
 *   bufxa - buffer with a drive
 * 
 *****************************************************************************/

module dffr (q,d,clk,rstn);
  input	 d,clk,rstn;
  output q;
  reg	 q;

always @(posedge clk or negedge rstn)
  begin
    if (rstn == 1'b0)
      q <= 1'b0;
    else
      q <= d;
  end // always @ (posedge clk or negedge rstn)
  
endmodule // dffr