core_adpt.h

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#if !defined(CORE_SAS_H)

#define CORE_SAS_H

#include "discover.h"
#include "core_ata.h"

#ifdef SUPPORT_SES
#include "core_ses.h"
#endif

/* For some ATA HDD only supports 28 bit LBA DMA. This definition is only for them. */
#define CORE_MAX_TRANSFER_SIZE			(128*1024)
#define CORE_MAX_TRANSFER_SECTOR		(CORE_MAX_TRANSFER_SIZE/SECTOR_LENGTH)

#define MAX_PHYSICAL_PORT_NUMBER       8
#ifdef SUPPORT_I2C
#define MAX_VIRTUAL_PORT_NUMBER          1
#else
#define MAX_VIRTUAL_PORT_NUMBER          0
#endif
#define MAX_PORT_NUMBER                (MAX_PHYSICAL_PORT_NUMBER + MAX_VIRTUAL_PORT_NUMBER)

#define MAX_PHY_NUM             12
#define MAX_ROUTE_INDEX         256

#define MAX_DEVICE_ID           MV_MAX_HD_DEVICE_ID
#define MAX_PORT_ID             MAX_PORT_NUMBER
#define ID_NOT_MAPPED           0xff
#define MAX_EXPANDER_ID         MIN_EXPANDER_ID + MAX_EXPANDER_SUPPORTED_PERFORMANCE

#ifdef SUPPORT_PM
#define MIN_PM_ID			MAX_EXPANDER_ID
#define MAX_PM_ID			MIN_PM_ID + MAX_PM_SUPPORTED
#endif

#define MAX_RX_FIS_NUMBER      17
#define MAX_SMP_RESP_SIZE      1016
#define MAX_SSP_RESP_SENSE_SIZE      sizeof(MV_Sense_Data)
//#define MAX_DELV_QUEUE_SIZE      CORE_MAX_REQUEST_NUMBER
//#define MAX_CMPL_QUEUE_SIZE      CORE_MAX_REQUEST_NUMBER

//#define MAX_INTERNAL_REQ_COUNT      MAX_DEVICE_NUMBER
#define MIN_INTERNAL_REQ_COUNT      1

//#define MAX_SATA_SCRATCH_COUNT      MAX_DEVICE_NUMBER
#define MIN_SATA_SCRATCH_COUNT      1

//#define MAX_SMP_SCRATCH_COUNT      MAX_EXPANDER_NUMBER
#define MIN_SMP_SCRATCH_COUNT      1      // TBD 

#define SG_BUFFER_SINGLE_COUNT		HW_SG_ENTRY_MAX
#define SG_BUFFER_SIZE				(SG_BUFFER_SINGLE_COUNT * sizeof(MV_SG_Entry))
#define MIN_SG_BUFFER_COUNT			8					
#define MAX_SG_BUFFER_COUNT			512		
#define MAX_SG_BUFFER_COUNT_NO_XOR	256

//TBD: Checking the following naming
#define RX_FIS_SIZE         256
#define UNASSOCIATED_FIS_POOL_SIZE      1024
#define RX_FIS_POOL_SIZE      RX_FIS_SIZE*MAX_RX_FIS_NUMBER + UNASSOCIATED_FIS_POOL_SIZE

#ifndef SOFTWARE_XOR
/*
  XOR
*/
#define MAX_XOR_CMD_ENTRY                           16
//#define MAX_XOR_SG_ENTRY                            256

/* XOR Engine can handle only two target at a time. 
 * If only have one or two target, for B0 board, one XOR table is enough for one XOR request. */
#define MAX_XOR_TABLE_PER_XOR_REQUEST				((XOR_TARGET_SG_COUNT+1)/2)
#endif

#define SATA_SCRATCH_BUFFER_SIZE                    sizeof(ATA_Identify_Data)
#define SMP_SCRATCH_BUFFER_SIZE                     sizeof(SMPRequest)
#ifdef SUPPORT_SES
#   define SES_CONTROL_BUFFER_SIZE               SATA_SCRATCH_BUFFER_SIZE
#endif /* SUPPORT_SES */


/* #define DEVICE_TYPE_ATAPI                           MV_BIT(0)
#define DEVICE_TYPE_SSP                             MV_BIT(1)
#define DEVICE_TYPE_STP                             MV_BIT(2)
#define DEVICE_TYPE_SATA                            MV_BIT(3)
#define DEVICE_TYPE_SES                             MV_BIT(4)
#define DEVICE_TYPE_TAPE                            MV_BIT(5) */

#define DC_ATA                                      MV_BIT(0)
#define DC_SCSI                                     MV_BIT(1)
#define DC_SERIAL                                   MV_BIT(2)
#define DC_PARALLEL                                 MV_BIT(3)
#define DC_ATAPI                                    MV_BIT(4)

/* PD's Device type defined in SCSI-III specification (used by new driver) */
#define DT_DIRECT_ACCESS_BLOCK                      0x00
#define DT_SEQ_ACCESS                               0x01
#define DT_PRINTER                                  0x02
#define DT_PROCESSOR                                0x03
#define DT_WRITE_ONCE                               0x04
#define DT_CD_DVD                                   0x05
#define DT_OPTICAL_MEMORY                           0x07
#define DT_MEDIA_CHANGER                            0x08
#define DT_STORAGE_ARRAY_CTRL                       0x0C
/* an actual enclosure */
#define DT_ENCLOSURE                                0x0D
/* The following are defined by Marvell */
#define DT_EXPANDER                                 0x20
#define DT_PM                                       0x21
/* a device that provides some SES services (ie, Luigi) */
#define DT_SES_DEVICE                               0x22

/* Some macros to make device type easier to use */
#define IS_SSP(pDevice)		    ((pDevice->Connection & DC_SCSI) && (pDevice->Connection & DC_SERIAL) &&	\
								 !(pDevice->Connection & DC_ATA))
#define IS_STP(pDevice)			((pDevice->Connection & DC_SCSI) && (pDevice->Connection & DC_SERIAL) &&	\
								 (pDevice->Connection & DC_ATA))
#define IS_NATIVE_SATA(pDevice)	(!(pDevice->Connection & DC_SCSI) && (pDevice->Connection & DC_SERIAL) &&	\
								 (pDevice->Connection & DC_ATA))
#define IS_STP_OR_SATA(pDevice) ((pDevice->Connection & DC_ATA) && (pDevice->Connection & DC_SERIAL))
#define IS_ATAPI(pDevice)		((pDevice->Connection & DC_ATAPI) && (pDevice->Connection & DC_ATA))
#define IS_TAPE(pDevice)		(pDevice->Dev_Type == DT_SEQ_ACCESS)

/* Device initialization state */
#define DEVICE_STATE_IDLE                           0x0
#define DEVICE_STATE_PM_ENABLE_1                    0x1
#define DEVICE_STATE_PM_ENABLE_0                    0x2
#define DEVICE_STATE_SRST_1                         0x3
#define DEVICE_STATE_SRST_0                         0x4
#define DEVICE_STATE_RESET_DONE                     0x5
// SATA device states
#define DEVICE_STATE_IDENTIFY_DONE                  0x6
#define DEVICE_STATE_SET_UDMA_DONE                  0x7
#define DEVICE_STATE_SET_PIO_DONE                   0x8
#define DEVICE_STATE_ENABLE_WRITE_CACHE_DONE        0x9
#define DEVICE_STATE_ENABLE_READ_AHEAD_DONE         0xA
/* SAS device states */
#define DEVICE_STATE_INQUIRY_DONE                   0xB /* issue read capacity next */
#define DEVICE_STATE_INQUIRY_16_DONE                0xC         // issue read capacity 16 next
#define DEVICE_STATE_READ_CAPACITY_DONE             0xD
#   ifdef CORE_SAS_SUPPORT_ATA_COMMAND
#      define DEVICE_STATE_MODE_SENSE_DONE          0xE
#      define DEVICE_STATE_MODE_SELECT_DONE         0xF
#   endif /* CORE_SAS_SUPPORT_ATA_COMMAND */
// Device states
#define DEVICE_STATE_FORMAT_DONE					0x10
#define DEVICE_STATE_FORMAT_WRITE					0x11
#define DEVICE_STATE_FORMAT_VERIFY					0x12
#define DEVICE_STATE_PM_SOFTRESET					0x13
#define DEVICE_STATE_STARTSTOP_DONE					0x14
#define DEVICE_STATE_INIT_DONE                      0xFF

/* Device status */
#define DEVICE_STATUS_NO_DEVICE                     MV_BIT(0)
#define DEVICE_STATUS_EXISTING                      MV_BIT(1)
#define DEVICE_STATUS_FUNCTIONAL                    MV_BIT(2)

/* 3G and TCQ */
#define DEVICE_CAPACITY_48BIT_SUPPORTED             MV_BIT(0)
#define   DEVICE_CAPACITY_SMART_SUPPORTED           MV_BIT(1)
#define   DEVICE_CAPACITY_WRITECACHE_SUPPORTED      MV_BIT(2)
#define DEVICE_CAPACITY_NCQ_SUPPORTED               MV_BIT(3)
#define DEVICE_CAPACITY_RATE_1_5G                   MV_BIT(4)
#define DEVICE_CAPACITY_RATE_3G                     MV_BIT(5)   
#define DEVICE_CAPACITY_READLOGEXT_SUPPORTED        MV_BIT(6)
#define DEVICE_CAPACITY_READ_LOOK_AHEAD_SUPPORTED	MV_BIT(7)
#define DEVICE_CAPACITY_SMART_SELF_TEST_SUPPORTED	MV_BIT(8)


#define DEVICE_SETTING_SMART_ENABLED                MV_BIT(0)
#define DEVICE_SETTING_WRITECACHE_ENABLED           MV_BIT(1)
#define DEVICE_SETTING_PI_ENABLED                   MV_BIT(2)
#define DEVICE_SETTING_READ_LOOK_AHEAD				MV_BIT(3)

#define MapDeviceId(pCore,ID)       ( pCore->Device_Map[ID] )

#ifdef SUPPORT_PM
#define MapPortId(pCore,ID)         ( (MapDeviceId(pCore,ID)==ID_NOT_MAPPED) ? ID_NOT_MAPPED :							\
										((ID < MIN_EXPANDER_ID) ? (pCore->Devices[pCore->Device_Map[ID]].pPort->Id) :	\
										((ID < MIN_PM_ID) ? (pCore->Expanders[pCore->Device_Map[ID]].pPort->Id) :		\
										 (pCore->PMs[pCore->Device_Map[ID]].pPort->Id))))
#else /* SUPPORT_PM */
#define MapPortId(pCore,ID)         ( (MapDeviceId(pCore,ID)==ID_NOT_MAPPED) ? ID_NOT_MAPPED :							\
										((ID < MIN_EXPANDER_ID) ? (pCore->Devices[pCore->Device_Map[ID]].pPort->Id) :	\
										 (pCore->Expanders[pCore->Device_Map[ID]].pPort->Id) ))
#endif /* SUPPORT_PM */

#define MapPortEntry(pCore,ID)      ( pCore->Port_Map[ID] )

#define RX_FIS_D2H_REG				0x40   /* offset of D2H Register FIS data */
#define FIS_REG_H2D_SIZE_IN_DWORD	5

/*
  ========================================================================
  64xx chip registers
  ========================================================================
*/

#ifdef _OS_WINDOWS
#define   MV_PCI_BAR                                5
#else /* _OS_WINDOWS */
#define   MV_PCI_BAR                                4
#endif /* _OS_WINDOWS */

#define GEN_HOST_CONTROL_REG_START                  0x0
#define VENDOR_SPECIFIC_REG_START                   0xa0
#define SAS_PORT_REG_START                          0x100

enum {
/* GEN_HOST_CONTROL */
	/* global controller registers */
	HOST_CAP_REG         = 0x00,    /* host capabilities */
	HBA_CONTROL          = 0x04,   /* global host control */
	HBA_IRQ_STAT         = 0x08,    /* interrupt status */
	HOST_PORTS_IMPL_REG  = 0x0c,    /* bitmap of implemented ports */
	/* HOST_CAP_REG bits */
	HOST_CAP_64          = (1 << 31), /* PCI DAC (64-bit DMA) support */

	/* HBA_CONTROL bits */
	MV_HBA_RESET         = (1 << 0),
	MV_HBA_INT_ENABLE    = (1 << 1),

	HOST_RESET           = (1 << 0),  /* reset controller; self-clear */
	HOST_IRQ_EN          = (1 << 1),  /* global IRQ enable */
	HOST_CMPL_Q_EN       = (1 << 2),  /* global done queue enable */

        /* HBA_IRQ_STAT (0x08) bits */
	SAS_SATA_IRQ_PENDING = (1 << 0),
	XOR_IRQ_PENDING      = (1 << 4),
};

/* HOST_PORTS_IMPL_REG bits */
typedef struct _REG_HBA_PORTS_IMPL
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:16;
	MV_U32   XOR_PORTS_IMPL:8;
	MV_U32   PORTS_IMPL:8;
#else
	MV_U32   PORTS_IMPL:8;
	MV_U32   XOR_PORTS_IMPL:8;
	MV_U32   Reserved:16;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_HBA_PORTS_IMPL, *PREG_HBA_PORTS_IMPL;

enum {
	HOST_PORTS_IMPL0   = (1 << 0),  /* HOST port0 existing  */
	HOST_PORTS_IMPL1   = (1 << 1),  /* HOST port1 existing  */
	HOST_PORTS_IMPL2   = (1 << 2),  /* HOST port2 existing  */
	HOST_PORTS_IMPL3   = (1 << 3),  /* HOST port3 existing  */
	HOST_PORTS_IMPL4   = (1 << 4),  /* HOST port0 existing  */
	HOST_PORTS_IMPL5   = (1 << 5),  /* HOST port1 existing  */
	HOST_PORTS_IMPL6   = (1 << 6),  /* HOST port2 existing  */
	HOST_PORTS_IMPL7   = (1 << 7),  /* HOST port3 existing  */
	HOST_XOR_IMPL      = (1 << 8),  /* HOST XOR port existing  */

        /* VENDOR_SPECIFIC */
	/* vendor specific registers */
	VSR_PORT_TYPE_REG  = VENDOR_SPECIFIC_REG_START,/* port type register */

	/* VSR_PORT_TYPE bits */
	MODE_SAS_PORT0_MASK = (1 << 0),  /* SATA if 0 is set */
	MODE_SAS_PORT1_MASK = (1 << 1),
	MODE_SAS_PORT2_MASK = (1 << 2),
	MODE_SAS_PORT3_MASK = (1 << 3),
	MODE_SAS_PORT4_MASK = (1 << 4),
	MODE_SAS_PORT5_MASK = (1 << 5),
	MODE_SAS_PORT6_MASK = (1 << 6),
	MODE_SAS_PORT7_MASK = (1 << 7),
	MODE_SAS_SATA       = MODE_SAS_PORT0_MASK | MODE_SAS_PORT1_MASK |
	MODE_SAS_PORT2_MASK | MODE_SAS_PORT3_MASK |
	MODE_SAS_PORT4_MASK | MODE_SAS_PORT5_MASK |
	MODE_SAS_PORT6_MASK | MODE_SAS_PORT7_MASK,
	MODE_AUTO_DET_PORT0 = (1 << 8),
	MODE_AUTO_DET_PORT1 = (1 << 9),
	MODE_AUTO_DET_PORT2 = (1 << 10),
	MODE_AUTO_DET_PORT3 = (1 << 11),
	MODE_AUTO_DET_PORT4 = (1 << 12),
	MODE_AUTO_DET_PORT5 = (1 << 13),
	MODE_AUTO_DET_PORT6 = (1 << 14),
	MODE_AUTO_DET_PORT7 = (1 << 15),
	MODE_AUTO_DET_EN    = MODE_AUTO_DET_PORT0 | MODE_AUTO_DET_PORT1 |
	                      MODE_AUTO_DET_PORT2 | MODE_AUTO_DET_PORT3 |
	                      MODE_AUTO_DET_PORT4 | MODE_AUTO_DET_PORT5 |
	                      MODE_AUTO_DET_PORT6 | MODE_AUTO_DET_PORT7,
	SATA_TRGT_EN_PORT0  = (1 << 16),
	SATA_TRGT_EN_PORT1  = (1 << 17),
	SATA_TRGT_EN_PORT2  = (1 << 18),
	SATA_TRGT_EN_PORT3  = (1 << 19),
	SATA_TRGT_EN_PORT4  = (1 << 20),
	SATA_TRGT_EN_PORT5  = (1 << 21),
	SATA_TRGT_EN_PORT6  = (1 << 22),
	SATA_TRGT_EN_PORT7  = (1 << 23),

        /* obsolete - to be removed soon */
	SAS_ON_PORT0 =      (1L << 0),  /* port0 SAS existing  */
	SAS_ON_PORT1 =      (1L << 1),  /* port1 SAS existing  */
	SAS_ON_PORT2 =      (1L << 2),  /* port2 SAS existing  */
	SAS_ON_PORT3 =      (1L << 3),  /* port3 SAS existing  */
	AUTO_DETECT_PORT0 =   (1L << 8),  /* port0 use auto detect  */
	AUTO_DETECT_PORT1 =   (1L << 9),  /* port1 use auto detect  */
	AUTO_DETECT_PORT2 =   (1L << 10),  /* port2 use auto detect  */
	AUTO_DETECT_PORT3 =   (1L << 11),  /* port3 use auto detect  */
	SATA_TRGT_MODE =   (1L << 16),  /* HOST XOR port existing  */

/* SAS_PORT_COMMON_REG */
	/* SATA/SAS port common registers */
	COMMON_CONFIG           = 0x100, /* configuration register */
	COMMON_CONTROL           = 0x104, /* control register */
	COMMON_LST_ADDR           = 0x108, /* command list DMA addr */
	COMMON_LST_ADDR_HI      = 0x10c, /* command list DMA addr hi */
	COMMON_FIS_ADDR           = 0x110, /* FIS rx buf addr */
	COMMON_FIS_ADDR_HI      = 0x114, /* FIS rx buf addr hi */
	COMMON_WORK_ADDR        = 0x118, /* workarea buf addr */
	COMMON_WORK_ADDR_HI     = 0x11c, /* workarea buf addr hi */
	COMMON_DELV_Q_CONFIG    = 0x120, /* delivery queue configuration */
	COMMON_DELV_Q_ADDR      = 0x124, /* delivery queue base address */
	COMMON_DELV_Q_ADDR_HI   = 0x128, /* delivery queue base address hi */
	COMMON_DELV_Q_WR_PTR    = 0x12c, /* delivery queue write pointer */
	COMMON_DELV_Q_RD_PTR    = 0x130, /* delivery queue read pointer */
	COMMON_CMPL_Q_CONFIG    = 0x134, /* completion queue configuration */
	COMMON_CMPL_Q_ADDR      = 0x138, /* completion queue base address */
	COMMON_CMPL_Q_ADDR_HI   = 0x13c, /* completion queue base address hi */
	COMMON_CMPL_Q_WR_PTR    = 0x140, /* completion queue write pointer */
	COMMON_CMPL_Q_RD_PTR    = 0x144, /* completion queue read pointer */
	COMMON_COAL_CONFIG      = 0x148, /* interrupt coalescing config */
	COMMON_COAL_TIMEOUT     = 0x14c, /* interrupt coalescing time wait */
	COMMON_IRQ_STAT           = 0x150, /* interrupt status */
	COMMON_IRQ_MASK           = 0x154, /* interrupt enable/disable mask */
	COMMON_SRS_IRQ_STAT     = 0x158, /* SRS interrupt status */
	COMMON_SRS_IRQ_MASK     = 0x15c, /* SRS intr enable/disable mask */

	PORT_IRQ_STAT0      = 0x160, /* Port 0 interrupt status */
	PORT_IRQ_MASK0      = 0x164, /* Port 0 interrupt enable/disable mask */
	PORT_IRQ_STAT1      = 0x168, /* Port 1 interrupt status */
	PORT_IRQ_MASK1      = 0x16c, /* Port 1 interrupt enable/disable mask */
	PORT_IRQ_STAT2      = 0x170, /* Port 2 interrupt status */
	PORT_IRQ_MASK2      = 0x174, /* Port 2 interrupt enable/disable mask */
	PORT_IRQ_STAT3      = 0x178, /* Port 3 interrupt status */
	PORT_IRQ_MASK3      = 0x17c, /* Port 3 interrupt enable/disable mask */

	PORT_PHY_CONTROL0  = 0x180, /* port 0 serial status/control */
	PORT_PHY_CONTROL1  = 0x184, /* port 1 serial status/control */
	PORT_PHY_CONTROL2  = 0x188, /* port 2 serial status/control */
	PORT_PHY_CONTROL3  = 0x18c, /* port 3 serial status/control */

	COMMON_CMD_ADDR      = 0x1b8, /* Command Address */
	COMMON_CMD_DATA      = 0x1bc, /* Command Data */

	PORT_CONFIG_ADDR0  = 0x1c0, /* Port 0 config address */
	PORT_CONFIG_DATA0  = 0x1c4, /* Port 0 config data */
	PORT_CONFIG_ADDR1  = 0x1c8, /* Port 1 config address */
	PORT_CONFIG_DATA1  = 0x1cc, /* Port 1 config data */
	PORT_CONFIG_ADDR2  = 0x1d0, /* Port 2 config address */
	PORT_CONFIG_DATA2  = 0x1d4, /* Port 2 config data */
	PORT_CONFIG_ADDR3  = 0x1d8, /* Port 3 config address */
	PORT_CONFIG_DATA3  = 0x1dc, /* Port 3 config data */

	PORT_VSR_ADDR0      = 0x1e0, /* port 0 Vendor Specific Register addr */
	PORT_VSR_DATA0      = 0x1e4, /* port 0 Vendor Specific Register Data */
	PORT_VSR_ADDR1      = 0x1e8, /* port 1 Vendor Specific Register addr */
	PORT_VSR_DATA1      = 0x1ec, /* port 1 Vendor Specific Register Data */
	PORT_VSR_ADDR2      = 0x1f0, /* port 2 Vendor Specific Register addr */
	PORT_VSR_DATA2      = 0x1f4, /* port 2 Vendor Specific Register Data */
	PORT_VSR_ADDR3      = 0x1f8, /* port 3 Vendor Specific Register addr */
	PORT_VSR_DATA3      = 0x1fc, /* port 3 Vendor Specific Register Data */

/* for 6480 */
	PORT_IRQ_STAT4      = 0x200, /* Port 4 interrupt status */
	PORT_IRQ_MASK4      = 0x204, /* Port 4 interrupt enable/disable mask */
	PORT_IRQ_STAT5      = 0x208, /* Port 5 interrupt status */
	PORT_IRQ_MASK5      = 0x20c, /* Port 5 interrupt enable/disable mask */
	PORT_IRQ_STAT6      = 0x210, /* Port 6 interrupt status */
	PORT_IRQ_MASK6      = 0x214, /* Port 6 interrupt enable/disable mask */
	PORT_IRQ_STAT7      = 0x218, /* Port 7 interrupt status */