core_adpt.h

来自「6440linuxDriver的源代码」· C头文件 代码 · 共 1,872 行 · 第 1/5 页

	CMD_XOR_MEM_BIST_STATUS   = 0x164, /* XOR Memroy BIST Status */
	CMD_DMA_MEM_BIST_CONTROL  = 0x168, /* DMA Memory BIST Control */
	CMD_DMA_MEM_BIST_STATUS   = 0x16c, /* DMA Memory BIST Status */
	CMD_PORT_MEM_BIST_CONTROL = 0x170, /* Port Memory BIST Control */
	CMD_PORT_MEM_BIST_STATUS0 = 0x174, /* Port Memory BIST Status 0 */
	CMD_PORT_MEM_BIST_STATUS1 = 0x178, /* Port Memory BIST Status 1 */
	CMD_STP_MEM_BIST_CONTROL  = 0x17c, /* STP Memory BIST Control */
	CMD_STP_MEM_BIST_STATUS0  = 0x180, /* STP Memory BIST Status 0 */
	CMD_STP_MEM_BIST_STATUS1  = 0x184, /* STP Memory BIST Status 1 */
	CMD_RESET_COUNT           = 0x188, /* Reset Count */
	CMD_MONTR_DATA_SEL        = 0x18C, /* Monitor Data/Select */
	CMD_PLL_PHY_CONFIG        = 0x190, /* PLL/PHY Configuration */
	CMD_PHY_CONTROL           = 0x194, /* PHY Control and Status */
	CMD_PHY_TEST_COUNT0       = 0x198, /* Phy Test Count 0 */
	CMD_PHY_TEST_COUNT1       = 0x19C, /* Phy Test Count 1 */
	CMD_PHY_TEST_COUNT2       = 0x1A0, /* Phy Test Count 2 */
	CMD_APP_ERR_CONFIG        = 0x1A4, /* Application Error Configuration */
	CMD_PND_FIFO_CONTROL0     = 0x1A8, /* Pending FIFO Control 0 */
	CMD_HOST_CONTROL          = 0x1AC, /* Host Control Status */
	CMD_HOST_WR_DATA          = 0x1B0, /* Host Write Data */
	CMD_HOST_RD_DATA          = 0x1B4, /* Host Read Data */
	CMD_PHY_MODE_21           = 0x1B8, /* Phy Mode 21 */
	CMD_SL_MODE0              = 0x1BC, /* SL Mode 0 */
	CMD_SL_MODE1              = 0x1C0, /* SL Mode 1 */
	CMD_PND_FIFO_CONTROL1     = 0x1C4, /* Pending FIFO Control 1 */
	CMD_PORT_ACTIVE16         = 0x240, /* Command Active 16 */
	CMD_PORT_ACTIVE17         = 0x244, /* Command Active 17 */
	CMD_PORT_ACTIVE18         = 0x248, /* Command Active 18 */
	CMD_PORT_ACTIVE19         = 0x24C, /* Command Active 19 */
	CMD_PORT_ACTIVE20         = 0x250, /* Command Active 20 */
	CMD_PORT_ACTIVE21         = 0x254, /* Command Active 21 */
	CMD_PORT_ACTIVE22         = 0x258, /* Command Active 22 */
	CMD_PORT_ACTIVE23         = 0x25C, /* Command Active 23 */
	CMD_PORT_ACTIVE24         = 0x260, /* Command Active 24 */
	CMD_PORT_ACTIVE25         = 0x264, /* Command Active 25 */
	CMD_PORT_ACTIVE26         = 0x268, /* Command Active 26 */
	CMD_PORT_ACTIVE27         = 0x26C, /* Command Active 27 */
	CMD_PORT_ACTIVE28         = 0x270, /* Command Active 28 */
	CMD_PORT_ACTIVE29         = 0x274, /* Command Active 29 */
	CMD_PORT_ACTIVE30         = 0x278, /* Command Active 30 */
	CMD_PORT_ACTIVE31         = 0x27C, /* Command Active 31 */
	CMD_SATA_TFDATA16         = 0x280, /* SATA Register Set 16 Task File Data */
	CMD_SATA_TFDATA17         = 0x284, /* SATA Register Set 17 Task File Data */
	CMD_SATA_TFDATA18         = 0x288, /* SATA Register Set 18 Task File Data */
	CMD_SATA_TFDATA19         = 0x28C, /* SATA Register Set 19 Task File Data */
	CMD_SATA_TFDATA20         = 0x290, /* SATA Register Set 20 Task File Data */
	CMD_SATA_TFDATA21         = 0x294, /* SATA Register Set 21 Task File Data */
	CMD_SATA_TFDATA22         = 0x298, /* SATA Register Set 22 Task File Data */
	CMD_SATA_TFDATA23         = 0x29C, /* SATA Register Set 23 Task File Data */
	CMD_SATA_TFDATA24         = 0x2A0, /* SATA Register Set 24 Task File Data */
	CMD_SATA_TFDATA25         = 0x2A4, /* SATA Register Set 25 Task File Data */
	CMD_SATA_TFDATA26         = 0x2A8, /* SATA Register Set 26 Task File Data */
	CMD_SATA_TFDATA27         = 0x2AC, /* SATA Register Set 27 Task File Data */
	CMD_SATA_TFDATA28         = 0x2B0, /* SATA Register Set 28 Task File Data */
	CMD_SATA_TFDATA29         = 0x2B4, /* SATA Register Set 29 Task File Data */
	CMD_SATA_TFDATA30         = 0x2B8, /* SATA Register Set 30 Task File Data */
	CMD_SATA_TFDATA31         = 0x2BC, /* SATA Register Set 31 Task File Data */
	CMD_SATA_ASSOC16          = 0x2C0, /* SATA Reg Set 16 Association */
	CMD_SATA_ASSOC17          = 0x2C4, /* SATA Reg Set 17 Association */
	CMD_SATA_ASSOC18          = 0x2C8, /* SATA Reg Set 18 Association */
	CMD_SATA_ASSOC19          = 0x2CC, /* SATA Reg Set 19 Association */
	CMD_SATA_ASSOC20          = 0x2D0, /* SATA Reg Set 20 Association */
	CMD_SATA_ASSOC21          = 0x2D4, /* SATA Reg Set 21 Association */
	CMD_SATA_ASSOC22          = 0x2D8, /* SATA Reg Set 22 Association */
	CMD_SATA_ASSOC23          = 0x2DC, /* SATA Reg Set 23 Association */
	CMD_SATA_ASSOC24          = 0x2E0, /* SATA Reg Set 24 Association */
	CMD_SATA_ASSOC25          = 0x2E4, /* SATA Reg Set 25 Association */
	CMD_SATA_ASSOC26          = 0x2E8, /* SATA Reg Set 26 Association */
	CMD_SATA_ASSOC27          = 0x2EC, /* SATA Reg Set 27 Association */
	CMD_SATA_ASSOC28          = 0x2F0, /* SATA Reg Set 28 Association */
	CMD_SATA_ASSOC29          = 0x2F4, /* SATA Reg Set 29 Association */
	CMD_SATA_ASSOC30          = 0x2F8, /* SATA Reg Set 30 Association */
	CMD_SATA_ASSOC31          = 0x2FC, /* SATA Reg Set 31 Association */
};

/* CMD_SATA_TFDATA bits */
typedef struct _REG_CMD_SATA_TFDATA_SLOT
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   E_STAT:8;
	MV_U32   SLT_NMBR:5;
	MV_U32   SET_DVC_BTS:1;
	MV_U32   PIO_SET_FIS:1;
	MV_U32   REG_DEV_HST_FIS:1;
	MV_U32   ERR_REG:8;
	MV_U32   STAT_REG:8;
#else
	MV_U32   STAT_REG:8;
	MV_U32   ERR_REG:8;
	MV_U32   REG_DEV_HST_FIS:1;
	MV_U32   PIO_SET_FIS:1;
	MV_U32   SET_DVC_BTS:1;
	MV_U32   SLT_NMBR:5;
	MV_U32   E_STAT:8;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_SATA_TFDATA_SLOT, *PREG_CMD_SATA_TFDATA_SLOT;

typedef struct _REG_CMD_SATA_TFDATA_PM
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   E_STAT:8;
	MV_U32   BIT_WISE_PRT:4;
	MV_U32   Reserved:1;
	MV_U32   SET_DEV_BIT_FIS:1;
	MV_U32   PIO_SET_FIS:1;
	MV_U32   REG_DEV_HST_FIS:1;
	MV_U32   ERR_REG:8;
	MV_U32   STAT_REG:8;
#else
	MV_U32   STAT_REG:8;
	MV_U32   ERR_REG:8;
	MV_U32   REG_DEV_HST_FIS:1;
	MV_U32   PIO_SET_FIS:1;
	MV_U32   SET_DEV_BIT_FIS:1;
	MV_U32   Reserved:1;
	MV_U32   BIT_WISE_PRT:4;
	MV_U32   E_STAT:8;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_SATA_TFDATA_PM, *PREG_CMD_SATA_TFDATA_PM;

/* CMD_SATA_ASSOC bits */
typedef struct _REG_CMD_SATA_ASSOC
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:10;
	MV_U32   PHY_NM:2;
	MV_U32   PM:4;
	MV_U32   ICT:16;
#else
	MV_U32   ICT:16;
	MV_U32   PM:4;
	MV_U32   PHY_NM:2;
	MV_U32   Reserved:10;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_SATA_ASSOC, *PREG_CMD_SATA_ASSOC;

/* CMD_CMRST_OOB_DET bits */
typedef struct _REG_CMD_CMRST_OOB_DET
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:16;
	MV_U32   COMRST_SHORT:8;
	MV_U32   COMRST_LONG:8;
#else
	MV_U32   COMRST_LONG:8;
	MV_U32   COMRST_SHORT:8;
	MV_U32   Reserved:16;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_CMRST_OOB_DET, *PREG_CMD_CMRST_OOB_DET;

/* CMD_CMWK_OOB_DET bits */
typedef struct _REG_CMD_CMWK_OOB_DET
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:16;
	MV_U32   COMWAKE_SHORT:8;
	MV_U32   COMWAKE_LONG:8;
#else
	MV_U32   COMWAKE_LONG:8;
	MV_U32   COMWAKE_SHORT:8;
	MV_U32   Reserved:16;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_CMWK_OOB_DET, *PREG_CMD_CMWK_OOB_DET;

/* CMD_CMSAS_OOB_DET bits */
typedef struct _REG_CMD_CMSAS_OOB_DET
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:16;
	MV_U32   COMSAS_SHORT:8;
	MV_U32   COMSAS_LONG:8;
#else
	MV_U32   COMSAS_LONG:8;
	MV_U32   COMSAS_SHORT:8;
	MV_U32   Reserved:16;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_CMSAS_OOB_DET, *PREG_CMD_CMSAS_OOB_DET;

/* CMD_BRST_OOB_DET bits */
typedef struct _REG_CMD_BRST_OOB_DET
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:16;
	MV_U32   BURST_SHORT:8;
	MV_U32   BURST_LONG:8;
#else
	MV_U32   BURST_LONG:8;
	MV_U32   BURST_SHORT:8;
	MV_U32   Reserved:16;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_BRST_OOB_DET, *PREG_CMD_BRST_OOB_DET;

/* CMD_OOB_SPACE bits */
typedef struct _REG_CMD_OOB_SPACE
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:12;
	MV_U32   COMSAS_SPACE:10;
	MV_U32   COMWAKE_SPACE:10;
	MV_U32   COMRESET_SPACE:10;
#else
	MV_U32   COMRESET_SPACE:10;
	MV_U32   COMWAKE_SPACE:10;
	MV_U32   COMSAS_SPACE:10;
	MV_U32   Reserved:12;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_OOB_SPACE, *PREG_CMD_OOB_SPACE;

/* CMD_OOB_BURST bits */
typedef struct _REG_CMD_OOB_BURST
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:17;
	MV_U32   BURST_CONT:1;
	MV_U32   BURST_NM:7;
	MV_U32   BURST_LNGTH:7;
#else
	MV_U32   BURST_LNGTH:7;
	MV_U32   BURST_NM:7;
	MV_U32   BURST_CONT:1;
	MV_U32   Reserved:17;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_OOB_BURST, *PREG_CMD_OOB_BURST;

/* CMD_PHY_TIMER bits */
typedef struct _REG_CMD_PHY_TIMER
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   HOTPLG_TMR_SEL:3;
	MV_U32   SL_RCVRY_TMR_SEL:3;
	MV_U32   PA_RCVRY_TMR_SEL:3;
	MV_U32   DEVICE_TMR_SEL:2;
	MV_U32   HOST_TMR_SEL:2;
	MV_U32   COMSAS_DTCT_TMR_SEL:2;
	MV_U32   RCDT_TMR_SEL:2;
	MV_U32   SNTT_TMR_SEL:2;
	MV_U32   SNLT_TMR_SEL:2;
	MV_U32   DSBL_GT_DATA_VLD_SQ:1;
	MV_U32   Reserved1:1;
	MV_U32   RST_TX_DLY_SEL:2;
	MV_U32   RST_RX_DLY_SEL:2;
	MV_U32   RST_DTL_DLY_SEL:2;
	MV_U32   SPD_CHG_RST_TX_DSBL:1;
	MV_U32   SPD_CHG_RST_RX_DSBL:1;
	MV_U32   SPD_CHG_RST_DTL_DSBL:1;
#else
	MV_U32   SPD_CHG_RST_DTL_DSBL:1;
	MV_U32   SPD_CHG_RST_RX_DSBL:1;
	MV_U32   SPD_CHG_RST_TX_DSBL:1;
	MV_U32   RST_DTL_DLY_SEL:2;
	MV_U32   RST_RX_DLY_SEL:2;
	MV_U32   RST_TX_DLY_SEL:2;
	MV_U32   Reserved1:1;
	MV_U32   DSBL_GT_DATA_VLD_SQ:1;
	MV_U32   SNLT_TMR_SEL:2;
	MV_U32   SNTT_TMR_SEL:2;
	MV_U32   RCDT_TMR_SEL:2;
	MV_U32   COMSAS_DTCT_TMR_SEL:2;
	MV_U32   HOST_TMR_SEL:2;
	MV_U32   DEVICE_TMR_SEL:2;
	MV_U32   PA_RCVRY_TMR_SEL:3;
	MV_U32   SL_RCVRY_TMR_SEL:3;
	MV_U32   HOTPLG_TMR_SEL:3;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_PHY_TIMER, *PREG_CMD_PHY_TIMER;

/* CMD_PHY_CONFIG0 bits */
typedef struct _REG_CMD_PHY_CONFIG0
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   HST_ALGN_CNT:7;
	MV_U32   DEV_WAIT_ALGN_CNT:7;
	MV_U32   ALGN0_CNT_SEL:6;
	MV_U32   ALGN1_CNT_SEL:6;
	MV_U32   BYPASS_OOB:1;
	MV_U32   DSBL_HOT_PLUG:1;
	MV_U32   Reserved:4;
#else
	MV_U32   Reserved:4;
	MV_U32   DSBL_HOT_PLUG:1;
	MV_U32   BYPASS_OOB:1;
	MV_U32   ALGN1_CNT_SEL:6;
	MV_U32   ALGN0_CNT_SEL:6;
	MV_U32   DEV_WAIT_ALGN_CNT:7;
	MV_U32   HST_ALGN_CNT:7;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_PHY_CONFIG0, *PREG_CMD_PHY_CONFIG0;

/* CMD_PHY_CONFIG1 bits */
typedef struct _REG_CMD_PHY_CONFIG1
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   ALGN_DET_MIN_CNT:16;
	MV_U32   Reserved:8;
	MV_U32   ALGN_INSRT_ENBL:1;
	MV_U32   ALGN_INSRT_CNT:7;
#else
	MV_U32   ALGN_INSRT_CNT:7;
	MV_U32   ALGN_INSRT_ENBL:1;
	MV_U32   Reserved:8;
	MV_U32   ALGN_DET_MIN_CNT:16;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_PHY_CONFIG1, *PREG_CMD_PHY_CONFIG1;

/* CMD_SAS_CONTROL0 bits */
typedef struct _REG_CMD_SAS_CONTROL0
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:1;
	MV_U32   NO_PRIM_INSRT:1;
	MV_U32   ALIGN_2048:1;
	MV_U32   TRNS_DT_INTLCK:1;
	MV_U32   TRNS_CRC_CFFCNT:1;
	MV_U32   TRNS_SCR_CFFCNT:1;
	MV_U32   RCV_CRC_CFFCNT:1;
	MV_U32   RCV_SCR_CFFCNT:1;
	MV_U32   US_CNT_TMR:8;
	MV_U32   ITNL_TMR_VAL:16;
#else
	MV_U32   ITNL_TMR_VAL:16;
	MV_U32   US_CNT_TMR:8;
	MV_U32   RCV_SCR_CFFCNT:1;
	MV_U32   RCV_CRC_CFFCNT:1;
	MV_U32   TRNS_SCR_CFFCNT:1;
	MV_U32   TRNS_CRC_CFFCNT:1;
	MV_U32   TRNS_DT_INTLCK:1;
	MV_U32   ALIGN_2048:1;
	MV_U32   NO_PRIM_INSRT:1;
	MV_U32   Reserved:1;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_SAS_CONTROL0, *PREG_CMD_SAS_CONTROL0;

/* CMD_SAS_CONTROL1 bits */
typedef struct _REG_CMD_SAS_CONTROL1
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:16;
	MV_U32   NON_DATA_RTRY_LMT:8;
	MV_U32   DATA_RTRY_LMT:8;
#else
	MV_U32   DATA_RTRY_LMT:8;
	MV_U32   NON_DATA_RTRY_LMT:8;
	MV_U32   Reserved:16;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_SAS_CONTROL1, *PREG_CMD_SAS_CONTROL1;

/* CMD_SAS_CONTROL2 bits */
typedef struct _REG_CMD_SAS_CONTROL2
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   DONE_TO_11_0:12;
	MV_U32   ACK_TMT_EN:1;
	MV_U32   ACK_TMT_TM:19;
#else
	MV_U32   ACK_TMT_TM:19;
	MV_U32   ACK_TMT_EN:1;
	MV_U32   DONE_TO_11_0:12;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_SAS_CONTROL2, *PREG_CMD_SAS_CONTROL2;

/* CMD_SAS_CONTROL3 bits */
typedef struct _REG_CMD_SAS_CONTROL3
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:4;
	MV_U32   CRDT_TO_EN:1;
	MV_U32   CRDT_TO_VAL:19;
	MV_U32   DONE_TO_EN:1;
	MV_U32   DONE_TO_18_12:7;
#else
	MV_U32   DONE_TO_18_12:7;
	MV_U32   DONE_TO_EN:1;
	MV_U32   CRDT_TO_VAL:19;
	MV_U32   CRDT_TO_EN:1;
	MV_U32   Reserved:4;