core_adpt.h

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} REG_XOR_DELV_Q_WR_PTR, *PREG_XOR_DELV_Q_WR_PTR;

/* XOR_DELV_Q_RD_PTR bits */
typedef struct _REG_XOR_DELV_Q_RD_PTR
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:20;
	MV_U32   DELV_QUEUE_RD_PTR:12;
#else
	MV_U32   DELV_QUEUE_RD_PTR:12;
	MV_U32   Reserved:20;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_XOR_DELV_Q_RD_PTR, *PREG_XOR_DELV_Q_RD_PTR;

enum {
        /* XOR_CMPL_Q_CONFIG (0x524) bits */
	XOR_CMPL_QUEUE_SIZE_MASK= (0xFFF << 0),
	XOR_CMPL_QUEUE_ENABLE   = (1 << 16),

        /* XOR_COAL_CONFIG (0x538) bits */
	XOR_INT_COAL_COUNT_MASK = (0x1FF << 0),
	XOR_INT_COAL_ENABLE     = (1 << 16),
	XOR_INT_COAL_COUNT      = (1 << 0),

        /* XOR_COAL_TIMEOUT (0x53c) bits */
	XOR_COAL_TIMER_MASK     = (0xFFFF << 0),
	XOR_COAL_TIMER_UNIT_1MS = (1 << 16), /* 1us, 6.67 ns if not set (0) */
};

/* XOR_IRQ_STAT bits */
typedef struct _REG_XOR_IRQ_STAT
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:19;
	MV_U32   XOR_ERR:1;      
	MV_U32   TBL_PRCSSD:1;      
	MV_U32   CMD_CMPL:1;
#else
	MV_U32   CMD_CMPL:1;
	MV_U32   TBL_PRCSSD:1;      
	MV_U32   XOR_ERR:1;      
	MV_U32   Reserved:19;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_XOR_IRQ_STAT, *PREG_XOR_IRQ_STAT;

enum {
        /* XOR_IRQ_MASK (0x544) bits */
	XOR_CMD_CMPL_IRQ    = (1 << 0),
	XOR_TBL_PROC_IRQ    = (1 << 1),
	XOR_ERR_IRQ         = (1 << 2),
};

/* XOR_ERR_CODE bits */
typedef struct _REG_XOR_ERR_CODE
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   ERR_TBL:16;      
	MV_U32   B1_ERR_PRD:4;
	MV_U32   Reserved2:3;      
	MV_U32   B1_ZR0_RSLT_CHK_ERR:1;
	MV_U32   B0_ERR_PRD:4;      
	MV_U32   Reserved1:3;      
	MV_U32   B0_ZR0_RSLT_CHK_ERR:1;
#else
	MV_U32   B0_ZR0_RSLT_CHK_ERR:1;
	MV_U32   Reserved1:3;      
	MV_U32   B0_ERR_PRD:4;      
	MV_U32   B1_ZR0_RSLT_CHK_ERR:1;
	MV_U32   Reserved2:3;      
	MV_U32   B1_ERR_PRD:4;
	MV_U32   ERR_TBL:16;      
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_XOR_ERR_CODE, *PREG_XOR_ERR_CODE;


/*
 * Hardware related format. Never change their size. Must follow hardware 
 * specification.
 */

/* for command list */
typedef struct _MV_Command_Header
{
#if __MV_BIG_ENDIAN_BITFIELD__
/* DWORD 0 */
	MV_U32   PRD_Entry_Count : 16;
	MV_U32   SSP_SSPFrameType : 3;
/* SSP only, 0-frame type set by HW, 1-frame type given by SSP_SSPFrameType */
	MV_U32   SSP_SSPPassThru : 1;
	/* SSP only, generate Burst without waiting for XFER-RDY */
	MV_U32   SSP_FirstBurst : 1;
	MV_U32   SSP_VerifyDataLen : 1;   /* SSP only, verify Data length */
	/* SSP only, set if enabling SSP transport layer retry */
	MV_U32   SSP_Retry : 1;   
	/* SSP only, set if protection information record present */
	MV_U32   ProtectInfoRecord : 1;
	MV_U32   Reset: 1;   /* SATA only, set if it is for device reset */
	/* SATA only, set if it is a first party DMA command */
	MV_U32   First_DMA : 1;   
	MV_U32   ATAPI : 1;   /* SATA only, set if it is a ATAPI PIO */
	MV_U32   BIST : 1;   /* SATA only, set if it is a BIST FIS */
	MV_U32   PM_Port : 4;   /* Port Multiplier field in command FIS */

/* DWORD 1 */
	MV_U32   Reserved2 : 7;
/* max response frame length in DW, HW will put in status buffer structure */
	MV_U32   MaxRspFrameLength : 9;
	MV_U32   Reserved1 : 6;
	/* command frame length in DW, including frame length, excluding CRC */
	MV_U32   FrameLength : 10;

/* DWORD 2 */
	/* Target Port Transfer Tag, for target to tag multiple XFER_RDY */
	MV_U32   TargetTag : 16;
	MV_U32   Tag : 16;   /* command tag */
#else /*  __MV_BIG_ENDIAN_BITFIELD__ */
/* DWORD 0 */
	MV_U32   PM_Port : 4;         /* Port Multiplier field in command FIS */
	MV_U32   BIST : 1;            /* SATA only, set if it is a BIST FIS */
	MV_U32   ATAPI : 1;            /* SATA only, set if it is a ATAPI PIO */
	MV_U32   First_DMA : 1;         /* SATA only, set if it is a first party DMA command */
	MV_U32   Reset: 1;            /* SATA only, set if it is for device reset */
	MV_U32   ProtectInfoRecord : 1;   /* SSP only, set if protection information record present */
	MV_U32   SSP_Retry : 1;         /* SSP only, set if enabling SSP transport layer retry */
	MV_U32   SSP_VerifyDataLen : 1;   /* SSP only, verify Data length */
	MV_U32   SSP_FirstBurst : 1;      /* SSP only, generate Burst without waiting for XFER-RDY */
	MV_U32   SSP_SSPPassThru : 1;   /* SSP only, 0-frame type set by HW, 1-frame type given by SSP_SSPFrameType */
	MV_U32   SSP_SSPFrameType : 3;
	MV_U32   PRD_Entry_Count : 16;
/* DWORD 1 */
	MV_U32   FrameLength : 10;      /* command frame length in DW, including frame length, excluding CRC */
	MV_U32   Reserved1 : 6;
	MV_U32   MaxRspFrameLength : 9;   /* max response frame length in DW, HW will put in status buffer structure */
	MV_U32   Reserved2 : 7;
/* DWORD 2 */
	MV_U32   Tag : 16;            /* command tag */
	MV_U32   TargetTag : 16;         /* Target Port Transfer Tag, for target to tag multiple XFER_RDY */
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */

/* DWORD 3 */
	MV_U32   DataXferLen;         /* in bytes */      
/* DWORD 4 */
	MV_U32   Table_Address;
/* DWORD 5 */
	MV_U32   Table_Address_High;
/* DWORD 6 */
	MV_U32   OpenAddrFrame_Address;
/* DWORD 7 */
	MV_U32   OpenAddrFrame_Address_High;
/* DWORD 8 */
	MV_U32   StatusBuff_Address;
/* DWORD 9 */
	MV_U32   StatusBuff_Address_High;
/* DWORD 10 */
	MV_U32   PRD_Table_Address;
/* DWORD 11 */
	MV_U32   PRD_Table_Address_High;
/* DWORD 12-15 */
	MV_U32   Reserved[4];

} MV_Command_Header, *PMV_Command_Header;

/* SSP_SSPFrameType */
#define FRAME_TYPE_COMMAND         0x00
#define FRAME_TYPE_TASK            0x01
#define FRAME_TYPE_XFER_RDY         0x04 /* Target mode */
#define FRAME_TYPE_RESPONSE         0x05 /* Target mode */
#define FRAME_TYPE_RD_DATA         0x06 /* Target mode */
#define FRAME_TYPE_RD_DATA_RESPONSE   0x07 /* Target mode, read data after response frame */
/* Tag */
#define SSP_I_HEADR_TAG_MASK      0xfe00   /* lower 9 bits from HW command slot */
#define SSP_T_HEADR_TAG_MASK      0xffff
#define STP_HEADR_TAG_MASK         0x001f   /* NCQ uses lower 5 bits  */
/* TargetTag */
#define SSP_T_HEADR_TGTTAG_MASK      0xfe00   /* lower 9 bits from HW command slot */

/* for command table */
/* SSP frame header */
typedef struct _SSP_Frame_Header
{
	MV_U8   Frame_Type;
	MV_U8   Hashed_Dest_SAS_Addr[3];
	MV_U8   Reseved1;
	MV_U8   Hashed_Src_SAS_Addr[3];
	MV_U8   Reseved2[2];
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U8   Reserved3:5;
	MV_U8   RetryData:1;   /* set in XFER_RDY to allow ReTx Data frames */
	MV_U8   ReTxed:1;   /* set in TASK/XFER_RDY/RESPONSE frames indicating this is a re-txed */
	MV_U8   CDP:1;      /* Change Data Pointer */

	MV_U8   Reserved4:6;
	MV_U8   NumberOfFillBytes:2;
#else /* __MV_BIG_ENDIAN_BITFIELD__ */
	MV_U8   CDP:1;         /* Change Data Pointer */
	MV_U8   ReTxed:1;      /* set in TASK/XFER_RDY/RESPONSE frames indicating this is a re-txed */
	MV_U8   RetryData:1;   /* set in XFER_RDY to allow ReTx Data frames */
	MV_U8   Reserved3:5;

	MV_U8   NumberOfFillBytes:2;
	MV_U8   Reserved4:6;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
	MV_U8   Reserved5[4];
	MV_U16   Tag;         /* command tag */
	MV_U16   TargetTag;      /* Target Port Transfer Tag, for target to tag multiple XFER_RDY */
	MV_U32   DataOffset;
}SSP_Frame_Header, *PSSP_Frame_Header;

/* SSP Command UI */
typedef struct _SSP_COMMAND_IU
{
	MV_U8   LUN[8];
	MV_U8   Reserved1;
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U8   AddCDBLen:6;      /* in DW */
	MV_U8   Reserved4:2;
	MV_U8   Reserved3;
	MV_U8   FirstBurst:1;
	MV_U8   Reserved2:4;
	MV_U8   TaskAttrib:3;
#else
	MV_U8   TaskAttrib:3;
	MV_U8   Reserved2:4;
	MV_U8   FirstBurst:1;
	MV_U8   Reserved3;
	MV_U8   Reserved4:2;
	MV_U8   AddCDBLen:6;      /* in DW */
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
	MV_U8   CDB[16];
/*   MV_U8   AddCDB[n] */
}SSP_COMMAND_IU, *PSSP_COMMAND_IU;

/* SSP TASK UI */
typedef struct _SSP_TASK_IU
{
	MV_U8   LUN[8];
	MV_U8   Reserved1[2];
	MV_U8   TaskFunction;
	MV_U8   Reserved2;
	MV_U16   Tag;
	MV_U8   Reserved3[14];
}SSP_TASK_IU, *PSSP_TASK_IU;
/*
 * Task Management Functions.
 */
#define ABORT_TASK_TMF      0x01
#define ABORT_TASK_SET_TMF   0x02
#define CLEAR_TASK_SET_TMF   0x04
#define LOGICAL_UNIT_RESET_TMF   0x08
#define CLEAR_ACA_TMF      0x40
#define QUERY_TASK_TMF      0x80

/* SSP XFER_RDY UI */
typedef struct _SSP_XFERRDY_IU
{
	MV_U32   DataOffset;
	MV_U32   DataLen;
	MV_U8   Reserved3[4];
}SSP_XFERRDY_IU, *PSSP_XFERRDY_IU;

/* SSP RESPONSE UI */
typedef struct _SSP_RESPONSE_IU
{
	MV_U8   Reserved1[10];
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U8   Reserved2:6;
	MV_U8   DataPres:2;
#else  /* __MV_BIG_ENDIAN_BITFIELD__ */
	MV_U8   DataPres:2;
	MV_U8   Reserved2:6;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
	MV_U8   Status;
	MV_U32   Reserved3;
	MV_U32   SenseDataLen;
	MV_U32   RespDataLen;
	MV_U8   Data[MAX_SSP_RESP_SENSE_SIZE];
/*   MV_U8   ResponseData[m] 
     or
     MV_U8   SenseData[n] */
}SSP_RESPONSE_IU, *PSSP_RESPONSE_IU;

/* DataPres */
#define NO_SENSE_RESPONSE   0x0
#define RESPONSE_ONLY      0x1
#define SENSE_ONLY         0x2
#define RESERVED         0x3

/* SSP Protection Information Record */
typedef struct _PROTECT_INFO_RECORD
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32 Reserved2:4;
	MV_U32 USR_DT_SZ:12;
	MV_U32 Reserved1:10;
	MV_U32 CHK_DSBL_MD:1;
	MV_U32 GRD_CHK:1;
	MV_U32 APP_CHK:1;
	MV_U32 REF_CHK:1;
	MV_U32 RMV_PROT:1;
	MV_U32 INSRT_PROT:1;

	MV_U32 LBRT;      /* Logical Block Reference Tag */

	MV_U32 LBAT_MASK:16;
	MV_U32 LBAT:16;      /* Logical Block Application Tag */
#else
	MV_U32 INSRT_PROT:1;
	MV_U32 RMV_PROT:1;
	MV_U32 REF_CHK:1;
	MV_U32 APP_CHK:1;
	MV_U32 GRD_CHK:1;
	MV_U32 CHK_DSBL_MD:1;
	MV_U32 Reserved1:10;
	MV_U32 USR_DT_SZ:12;
	MV_U32 Reserved2:4;

	MV_U32 LBRT;      /* Logical Block Reference Tag */

	MV_U32 LBAT:16;      /* Logical Block Application Tag */
	MV_U32 LBAT_MASK:16;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
}PROTECT_INFO_RECORD, *PPROTECT_INFO_RECORD;

/* SSP Command Table */
typedef struct _MV_SSP_Command_Table
{
	SSP_Frame_Header Frame_Header;
	union
	{
		struct {
			struct _SSP_COMMAND_IU commandIU;
			PROTECT_INFO_RECORD PIR;
		} command;
		struct _SSP_TASK_IU task;
		struct _SSP_XFERRDY_IU xfer_rdy;
		struct _SSP_RESPONSE_IU response;
	} data;
} MV_SSP_Command_Table, *PMV_SSP_Command_Table;

// SMP Command Table
typedef struct SMPRequest MV_SMP_Command_Table;

/* SATA STP Command Table */
typedef struct _MV_SATA_STP_Command_Table
{
	MV_U8   FIS[64];                        /* Command FIS */
	MV_U8   ATAPI_CDB[32];                     /* ATAPI CDB */
} MV_SATA_STP_Command_Table, *PMV_SATA_STP_Command_Table;

/* Open Address Frame */
typedef struct _OPEN_ADDRESS_FRAME
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U8   Initiator:1;
	MV_U8   Protocol:3;
	MV_U8   Frame_Type:4;

	MV_U8   Feature:4;
	MV_U8   Connect_Rate:4;
#else /* __MV_BIG_ENDIAN_BITFIELD__ */
	MV_U8   Frame_Type:4;
	MV_U8   Protocol:3;
	MV_U8   Initiator:1;

	MV_U8   Connect_Rate:4;
	MV_U8   Feature:4;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
	MV_U8   Connect_Tag[2];
	MV_U8   Dest_SAS_Addr[8];         
/* HW will generate Byte 12 after... */
	MV_U8   Src_SAS_Addr[8];
	MV_U8   Cmp_