core_adpt.h

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	PORT_IRQ_MASK7      = 0x21c, /* Port 7 interrupt enable/disable mask */

#define READ_PORT_IRQ_STAT(mmio,i) \
   ((i>3)?MV_REG_READ_DWORD(mmio,PORT_IRQ_STAT4+(i-4)*8):MV_REG_READ_DWORD(mmio,PORT_IRQ_STAT0+i*8)) 
#define WRITE_PORT_IRQ_STAT(mmio,i,tmp) \
   {if(i>3)MV_REG_WRITE_DWORD(mmio,PORT_IRQ_STAT4+(i-4)*8,tmp);else MV_REG_WRITE_DWORD(mmio,PORT_IRQ_STAT0+i*8,tmp);} 
#define READ_PORT_IRQ_MASK(mmio,i) \
   ((i>3)?MV_REG_READ_DWORD(mmio,PORT_IRQ_MASK4+(i-4)*8):MV_REG_READ_DWORD(mmio,PORT_IRQ_MASK0+i*8)) 
#define WRITE_PORT_IRQ_MASK(mmio,i,tmp) \
   {if(i>3)MV_REG_WRITE_DWORD(mmio,PORT_IRQ_MASK4+(i-4)*8,tmp);else MV_REG_WRITE_DWORD(mmio,PORT_IRQ_MASK0+i*8,tmp);}

	PORT_PHY_CONTROL4      = 0x220, /* port 4 serial status/control */
	PORT_PHY_CONTROL5      = 0x224, /* port 5 serial status/control */
	PORT_PHY_CONTROL6      = 0x228, /* port 6 serial status/control */
	PORT_PHY_CONTROL7      = 0x22c, /* port 7 serial status/control */

#define READ_PORT_PHY_CONTROL(mmio, i) \
   ((i>3)?MV_REG_READ_DWORD(mmio,PORT_PHY_CONTROL4+(i-4)*4):MV_REG_READ_DWORD(mmio,PORT_PHY_CONTROL0+i*4)) 

#define WRITE_PORT_PHY_CONTROL(mmio,i,tmp) \
   {if(i>3)MV_REG_WRITE_DWORD(mmio,PORT_PHY_CONTROL4+(i-4)*4,tmp);else MV_REG_WRITE_DWORD(mmio,PORT_PHY_CONTROL0+i*4,tmp);} 

	PORT_CONFIG_ADDR4      = 0x230, /* Port 4 config address */
	PORT_CONFIG_DATA4      = 0x234, /* Port 4 config data */
	PORT_CONFIG_ADDR5      = 0x238, /* Port 5 config address */
	PORT_CONFIG_DATA5      = 0x23c, /* Port 5 config data */
	PORT_CONFIG_ADDR6      = 0x240, /* Port 6 config address */
	PORT_CONFIG_DATA6      = 0x244, /* Port 6 config data */
	PORT_CONFIG_ADDR7      = 0x248, /* Port 7 config address */
	PORT_CONFIG_DATA7      = 0x24c, /* Port 7 config data */

#define READ_PORT_CONFIG_DATA(mmio,i) \
   ((i>3)?MV_REG_READ_DWORD(mmio,PORT_CONFIG_DATA4+(i-4)*8):MV_REG_READ_DWORD(mmio,PORT_CONFIG_DATA0+i*8)) 
#define WRITE_PORT_CONFIG_DATA(mmio,i,tmp) \
   {if(i>3)MV_REG_WRITE_DWORD(mmio,PORT_CONFIG_DATA4+(i-4)*8,tmp);else MV_REG_WRITE_DWORD(mmio,PORT_CONFIG_DATA0+i*8,tmp);} 
#define WRITE_PORT_CONFIG_ADDR(mmio,i,tmp) \
   {if(i>3)MV_REG_WRITE_DWORD(mmio,PORT_CONFIG_ADDR4+(i-4)*8,tmp);else MV_REG_WRITE_DWORD(mmio,PORT_CONFIG_ADDR0+i*8,tmp);} 

	PORT_VSR_ADDR4      = 0x250, /* port 4 Vendor Specific Register addr */
	PORT_VSR_DATA4      = 0x254, /* port 4 Vendor Specific Register Data */
	PORT_VSR_ADDR5      = 0x258, /* port 5 Vendor Specific Register addr */
	PORT_VSR_DATA5      = 0x25c, /* port 5 Vendor Specific Register Data */
	PORT_VSR_ADDR6      = 0x260, /* port 6 Vendor Specific Register addr */
	PORT_VSR_DATA6      = 0x264, /* port 6 Vendor Specific Register Data */
	PORT_VSR_ADDR7      = 0x268, /* port 7 Vendor Specific Register addr */
	PORT_VSR_DATA7      = 0x26c, /* port 7 Vendor Specific Register Data */

#define READ_PORT_VSR_DATA(mmio,i) \
   ((i>3)?MV_REG_READ_DWORD(mmio,PORT_VSR_DATA4+(i-4)*8):MV_REG_READ_DWORD(mmio,PORT_VSR_DATA0+i*8)) 
#define WRITE_PORT_VSR_DATA(mmio,i,tmp) \
   {if(i>3)MV_REG_WRITE_DWORD(mmio,PORT_VSR_DATA4+(i-4)*8,tmp);else MV_REG_WRITE_DWORD(mmio,PORT_VSR_DATA0+i*8,tmp);} 
#define WRITE_PORT_VSR_ADDR(mmio,i,tmp) \
   {if(i>3)MV_REG_WRITE_DWORD(mmio,PORT_VSR_ADDR4+(i-4)*8,tmp);else MV_REG_WRITE_DWORD(mmio,PORT_VSR_ADDR0+i*8,tmp);} 

	/* COMMON_CONFIG register bits */
	MV_CMD_TBL_BE       = (1 << 0),
	MV_OPEN_ADDR_BE     = (1 << 1),
	MV_RSPNS_FRAME_BE   = (1 << 2),
	MV_DATA_BE          = (1 << 3),
	MV_SAS_SATA_RST     = (1 << 5),
	EN_SATA_REG_16      = (1 << 16),
	EN_SATA_REG_17      = (1 << 17),
	EN_SATA_REG_18      = (1 << 18),
	EN_SATA_REG_19      = (1 << 19),
	EN_SATA_REG_20      = (1 << 20),
	EN_SATA_REG_21      = (1 << 21),
	EN_SATA_REG_22      = (1 << 22),
	EN_SATA_REG_23      = (1 << 23),
	EN_SATA_REG_24      = (1 << 24),
	EN_SATA_REG_25      = (1 << 25),
	EN_SATA_REG_26      = (1 << 26),
	EN_SATA_REG_27      = (1 << 27),
	EN_SATA_REG_28      = (1 << 28),
	EN_SATA_REG_29      = (1 << 29),
	EN_SATA_REG_30      = (1 << 30),
	EN_SATA_REG_31      = (1 << 31),


	/* pci config register */
	MV_PCI_REG_CMD      = 0x04,
	MV_PCI_REG_DEV_CTRL = 0xE8,
	MV_PCI_REG_PHY_CTRL = 0x40,
	MV_PCI_REG_MSI_CAP_ID = 0x50,
	MV_PCI_REG_MSI_CTRL = 0x52,
	MV_PCI_REG_VEN_UNIQ3= 0x60,
	MV_PCI_REG_PHY_CTRL2= 0x90,

	MV_PCI_IO_EN        = (1 << 0),
	MV_PCI_MEM_EN       = (1 << 1),
	MV_PCI_BM_EN        = (1 << 2),    /* enable bus master */
	MV_PCI_INT_DIS      = (1 << 10),   /* disable INTx for MSI_EN */
	MV_PCI_DEV_EN       = MV_PCI_IO_EN | MV_PCI_MEM_EN | MV_PCI_BM_EN,

	MV_PCI_MSI_EN       = (1 << 0),


	MV_PCI_RD_REQ_SIZE  = 0x4000,
	MV_PCI_RD_REQ_MASK  = 0x00007000,

	MV_PCI_PAD_TEST_MASK= 0xFF000000, /* Test Pad bits located in Vendor Unique 3*/

	MV_PCI_PHY_OFF      = (0xF << 12),
	MV_PCI_PHY_PWR_ON   = (0xF << 24),

        /* COMMON_CONTROL : port control/status bits (R104h) */
	EN_CMD_ISSUE        = (1 << 0),
	RESET_CMD_ISSUE     = (1 << 1),
	ERR_STOP_CMD_ISSUE  = (1 << 3),
	FIS_RCV_EN          = (1 << 4),
	CMD_CMPL_SELF_CLEAR = (1 << 5),
	CMD_CMPL_IRQ_MODE   = (1 << 5),   /* self-clear CMD_CMPL */
	RSPNS_RCV_EN        = (1 << 7),
	EN_SATA_RETRY       = (1 << 8),
	EN_PORT_0_XMT       = (1 << 12),
	EN_PORT_1_XMT       = (1 << 13),
	EN_PORT_2_XMT       = (1 << 14),
	EN_PORT_3_XMT       = (1 << 15),
	EN_SATA_REG_0       = (1 << 16),
	EN_SATA_REG_1       = (1 << 17),
	EN_SATA_REG_2       = (1 << 18),
	EN_SATA_REG_3       = (1 << 19),
	EN_SATA_REG_4       = (1 << 20),
	EN_SATA_REG_5       = (1 << 21),
	EN_SATA_REG_6       = (1 << 22),
	EN_SATA_REG_7       = (1 << 23),
	EN_SATA_REG_8       = (1 << 24),
	EN_SATA_REG_9       = (1 << 25),
	EN_SATA_REG_10      = (1 << 26),
	EN_SATA_REG_11      = (1 << 27),
	EN_SATA_REG_12      = (1 << 28),
	EN_SATA_REG_13      = (1 << 29),
	EN_SATA_REG_14      = (1 << 30),
	EN_SATA_REG_15      = (1 << 31),

	EN_PORT_XMT_START   = 12,
	EN_PORT_XMT_START2  = 8,

        /* COMMON_DELV_Q_CONFIG (R120h) bits */
	DELV_QUEUE_SIZE_MASK= (0xFFF << 0),
	DELV_QUEUE_ENABLE   = (1 << 16),

};

/* COMMON_DELV_Q_RD_PTR bits */
typedef struct _REG_COMMON_DELV_Q_RD_PTR
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:20;
	MV_U32   DELV_QUEUE_RD_PTR:12;
#else
	MV_U32   DELV_QUEUE_RD_PTR:12;
	MV_U32   Reserved:20;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_COMMON_DELV_Q_RD_PTR, *PREG_COMMON_DELV_Q_RD_PTR;

enum {
        /* COMMON_CMPL_Q_CONFIG (R134h) bits */
	CMPL_QUEUE_SIZE_MASK     = (0xFFF << 0),
	CMPL_QUEUE_ENABLE        = (1 << 16),
};

/* COMMON_CMPL_Q_WR_PTR bits */
typedef struct _REG_COMMON_CMPL_Q_WR_PTR
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:20;
	MV_U32   CMPLN_QUEUE_WRT_PTR:12;
#else
	MV_U32   CMPLN_QUEUE_WRT_PTR:12;
	MV_U32   Reserved:20;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_COMMON_CMPL_Q_WR_PTR, *PREG_COMMON_CMPL_Q_WR_PTR;

enum {
        /* COMMON_COAL_CONFIG (R148h) bits */
	INT_COAL_COUNT_MASK      = (0x1FF << 0),
	INT_COAL_ENABLE          = (1 << 16),

        /* COMMON_COAL_TIMEOUT (R14Ch) bits */
	COAL_TIMER_MASK          = (0xFFFF << 0),
	COAL_TIMER_UNIT_1MS      = (1 << 16),   /* 6.67 ns if set to 0 */

        /* COMMON_IRQ_STAT/MASK (R150h) bits */
	INT_CMD_CMPL               = (1 << 0),
	INT_CMD_CMPL_MASK          = (1 << 0),
	INT_CMD_ISSUE_STOPPED      = (1 << 1),
	INT_SRS                    = (1 << 3),
	INT_PORT_MASK_OFFSET       = 8,
	INT_PORT_MASK              = (0xFF << INT_PORT_MASK_OFFSET),
	INT_PORT_STOP_MASK_OFFSET  = 16,
	INT_PORT_STOP_MASK         = (0xFF << INT_PORT_STOP_MASK_OFFSET),
	INT_SLAVE_I2C              = (1 << 25),
	INT_MEM_PAR_ERR            = (1 << 26),
	INT_I2C                    = (1 << 31),
};

/* COMMON_SRS_IRQ_STAT/MASK bits */
typedef struct _REG_COMMON_SRS_IRQ_STAT
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:16;
	MV_U32   REG_SET_15_STPD:1;
	MV_U32   REG_SET_14_STPD:1;
	MV_U32   REG_SET_13_STPD:1;
	MV_U32   REG_SET_12_STPD:1;
	MV_U32   REG_SET_11_STPD:1;
	MV_U32   REG_SET_10_STPD:1;
	MV_U32   REG_SET_9_STPD:1;
	MV_U32   REG_SET_8_STPD:1;
	MV_U32   REG_SET_7_STPD:1;
	MV_U32   REG_SET_6_STPD:1;
	MV_U32   REG_SET_5_STPD:1;
	MV_U32   REG_SET_4_STPD:1;
	MV_U32   REG_SET_3_STPD:1;
	MV_U32   REG_SET_2_STPD:1;
	MV_U32   REG_SET_1_STPD:1;
	MV_U32   REG_SET_0_STPD:1;
#else
	MV_U32   REG_SET_0_STPD:1;
	MV_U32   REG_SET_1_STPD:1;
	MV_U32   REG_SET_2_STPD:1;
	MV_U32   REG_SET_3_STPD:1;
	MV_U32   REG_SET_4_STPD:1;
	MV_U32   REG_SET_5_STPD:1;
	MV_U32   REG_SET_6_STPD:1;
	MV_U32   REG_SET_7_STPD:1;
	MV_U32   REG_SET_8_STPD:1;
	MV_U32   REG_SET_9_STPD:1;
	MV_U32   REG_SET_10_STPD:1;
	MV_U32   REG_SET_11_STPD:1;
	MV_U32   REG_SET_12_STPD:1;
	MV_U32   REG_SET_13_STPD:1;
	MV_U32   REG_SET_14_STPD:1;
	MV_U32   REG_SET_15_STPD:1;
	MV_U32   Reserved:16;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_COMMON_SRS_IRQ_STAT, *PREG_COMMON_SRS_IRQ_STAT;


enum {
        /* PORT_IRQ_STAT/MASK (R160h) bits */
	PHY_RDY_CHNG_MASK         = (1 << 0),
	HRD_RES_DONE_MASK         = (1 << 1),
	PHY_ID_DONE_MASK          = (1 << 2),
	PHY_ID_FAIL_MASK          = (1 << 3),
	PHY_ID_TIMEOUT            = (1 << 4),
	HARD_RESET_RCVD_MASK      = (1 << 5),
	PORT_SEL_PRESENT_MASK     = (1 << 6),
	COMWAKE_RCVD_MASK         = (1 << 7),
	BRDCST_CHNG_RCVD_MASK     = (1 << 8),
	UNKNOWN_TAG_ERR           = (1 << 9),
	IU_TOO_SHRT_ERR           = (1 << 10),
	IU_TOO_LNG_ERR            = (1 << 11),
	PHY_RDY_CHNG_1_TO_0		  = (1 << 12),
	SIG_FIS_RCVD_MASK         = (1 << 16),
	BIST_ACTVT_FIS_RCVD_MASK  = (1 << 17),
	ASYNC_NTFCN_RCVD_MASK     = (1 << 18),
	UNASSOC_FIS_RCVD_MASK     = (1 << 19),
	STP_SATA_RX_ERR_MASK      = (1 << 20),
	STP_SATA_TX_ERR_MASK      = (1 << 21),
	STP_SATA_CRC_ERR_MASK     = (1 << 22),
	STP_SATA_DCDR_ERR_MASK    = (1 << 23),
	STP_SATA_PHY_DEC_ERR_MASK = (1 << 24),
	STP_SATA_SYNC_ERR_MASK    = (1 << 25),

	/* PORT_PHY_CONTROL/STATUS bits */
	MV_PHY_RESET                   = (1 << 0),
	MV_PHY_HARD_RESET_SEQ          = (1 << 1),
	MV_PHY_BRDCST_CHNG_NOTIFY      = (1 << 2),
	MV_SSP_RESET                   = (1 << 3),
	MV_SAS_LINK_EN                 = (1 << 4),
	MV_MIN_SPP_PHYS_LINK_RATE_MASK = (0xF << 8),
	MV_MAX_SPP_PHYS_LINK_RATE_MASK = (0xF << 12),
	MV_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = 16,
	MV_NEG_SPP_PHYS_LINK_RATE_MASK = (0xF << MV_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
	MV_PHY_READY_MASK              = (1 << 20),

/* Command Port Registers COMMON_CMD_ADDR, COMMON_CMD_DATA */
	/* command port issue register $i (slot 0-31) to (slot 480-511) */
	CMD_PORT_ISS0  = 0x00,
	CMD_PORT_ISS1  = 0x04,
	CMD_PORT_ISS2  = 0x08,
	CMD_PORT_ISS3  = 0x0c,
	CMD_PORT_ISS4  = 0x10,
	CMD_PORT_ISS5  = 0x14,
	CMD_PORT_ISS6  = 0x18,
	CMD_PORT_ISS7  = 0x1c,
	CMD_PORT_ISS8  = 0x20,
	CMD_PORT_ISS9  = 0x24,
	CMD_PORT_ISS10 = 0x28,
	CMD_PORT_ISS11 = 0x2c,
	CMD_PORT_ISS12 = 0x30,
	CMD_PORT_ISS13 = 0x34,
	CMD_PORT_ISS14 = 0x38,
	CMD_PORT_ISS15 = 0x3c,

	/* cmd port active register $i (slot 0-31) to (slot 480-511) */
	CMD_PORT_ACTIVE0  = 0x40, 
	CMD_PORT_ACTIVE1  = 0x44,
	CMD_PORT_ACTIVE2  = 0x48,
	CMD_PORT_ACTIVE3  = 0x4c,
	CMD_PORT_ACTIVE4  = 0x50,
	CMD_PORT_ACTIVE5  = 0x54,
	CMD_PORT_ACTIVE6  = 0x58,
	CMD_PORT_ACTIVE7  = 0x5c,
	CMD_PORT_ACTIVE8  = 0x60,
	CMD_PORT_ACTIVE9  = 0x64,
	CMD_PORT_ACTIVE10 = 0x68,
	CMD_PORT_ACTIVE11 = 0x6c,
	CMD_PORT_ACTIVE12 = 0x70,
	CMD_PORT_ACTIVE13 = 0x74,
	CMD_PORT_ACTIVE14 = 0x78,
	CMD_PORT_ACTIVE15 = 0x7c,

	/* SATA register set $i task file data register */
	CMD_SATA_TFDATA0  = 0x80,
	CMD_SATA_TFDATA1  = 0x84,
	CMD_SATA_TFDATA2  = 0x88,
	CMD_SATA_TFDATA3  = 0x8c,
	CMD_SATA_TFDATA4  = 0x90,
	CMD_SATA_TFDATA5  = 0x94,
	CMD_SATA_TFDATA6  = 0x98,
	CMD_SATA_TFDATA7  = 0x9c,
	CMD_SATA_TFDATA8  = 0xa0,
	CMD_SATA_TFDATA9  = 0xa4,
	CMD_SATA_TFDATA10 = 0xa8,
	CMD_SATA_TFDATA11 = 0xac,
	CMD_SATA_TFDATA12 = 0xb0,
	CMD_SATA_TFDATA13 = 0xb4,
	CMD_SATA_TFDATA14 = 0xb8,
	CMD_SATA_TFDATA15 = 0xbc,

	/* SATA register set $i association reg */
	CMD_SATA_ASSOC0     = 0xc0,
	CMD_SATA_ASSOC1     = 0xc4,
	CMD_SATA_ASSOC2     = 0xc8,
	CMD_SATA_ASSOC3     = 0xcc,
	CMD_SATA_ASSOC4     = 0xd0,
	CMD_SATA_ASSOC5     = 0xd4,
	CMD_SATA_ASSOC6     = 0xd8,
	CMD_SATA_ASSOC7     = 0xdc,
	CMD_SATA_ASSOC8     = 0xe0,
	CMD_SATA_ASSOC9     = 0xe4,
	CMD_SATA_ASSOC10  = 0xe8,
	CMD_SATA_ASSOC11  = 0xec,
	CMD_SATA_ASSOC12  = 0xf0,
	CMD_SATA_ASSOC13  = 0xf4,
	CMD_SATA_ASSOC14  = 0xf8,
	CMD_SATA_ASSOC15  = 0xfc,

	CMD_CMRST_OOB_DET         = 0x100, /* COMRESET OOB detect register */
	CMD_CMWK_OOB_DET          = 0x104, /* COMWAKE OOB detect register */
	CMD_CMSAS_OOB_DET         = 0x108, /* COMSAS OOB detect register */
	CMD_BRST_OOB_DET          = 0x10c, /* burst OOB detect register */
	CMD_OOB_SPACE             = 0x110, /* OOB space control register */
	CMD_OOB_BURST             = 0x114, /* OOB burst control register */
	CMD_PHY_TIMER             = 0x118, /* PHY timer control register */
	CMD_PHY_CONFIG0             = 0x11c, /* PHY config register 0 */
	CMD_PHY_CONFIG1             = 0x120, /* PHY config register 1 */
	CMD_SAS_CONTROL0          = 0x124, /* SAS control register 0 */
	CMD_SAS_CONTROL1          = 0x128, /* SAS control register 1 */
	CMD_SAS_CONTROL2          = 0x12c, /* SAS control register 2 */
	CMD_SAS_CONTROL3          = 0x130, /* SAS control register 3 */
	CMD_ID_TEST               = 0x134, /* ID test register */
	CMD_PL_TIMER              = 0x138, /* PL timer register */
	CMD_WD_TIMER              = 0x13c, /* WD timer register */
	CMD_PORT_SEL_COUNT        = 0x140, /* port selector count register */
	CMD_APP_MEM_CONTROL       = 0x144, /* Application Memory Control */
	CMD_XOR_MEM_CONTROL       = 0x148, /* XOR Block Memory Control */
	CMD_DMA_MEM_CONTROL       = 0x14c, /* DMA Block Memory Control */
	CMD_PORT_MEM_CONTROL0     = 0x150, /* Port Memory Control 0 */
	CMD_PORT_MEM_CONTROL1     = 0x154, /* Port Memory Control 1 */
	CMD_SATA_PORT_MEM_CONTROL0= 0x158, /* SATA Port Memory Control 0 */
	CMD_SATA_PORT_MEM_CONTROL1= 0x15c, /* SATA Port Memory Control 1 */
	CMD_XOR_MEM_BIST_CONTROL  = 0x160, /* XOR Memory BIST Control */