core_adpt.h

来自「6440linuxDriver的源代码」· C头文件 代码 · 共 1,872 行 · 第 1/5 页

#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_SAS_CONTROL3, *PREG_CMD_SAS_CONTROL3;

/* CMD_ID_TEST bits */
typedef struct _REG_CMD_ID_TEST
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:10;
	MV_U32   TX_ID_EN:1;
	MV_U32   HR_EN:1;
	MV_U32   ID_WT_EN:1;
	MV_U32   ID_FRM_RTRY_EN:1;
	MV_U32   ID_WT_TM:18;
#else
	MV_U32   ID_WT_TM:18;
	MV_U32   ID_FRM_RTRY_EN:1;
	MV_U32   ID_WT_EN:1;
	MV_U32   HR_EN:1;
	MV_U32   TX_ID_EN:1;
	MV_U32   Reserved:10;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_ID_TEST, *PREG_CMD_ID_TEST;

/* CMD_PL_TIMER bits */
typedef struct _REG_CMD_PL_TIMER
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   MAX_CONN_TM_LMT:16;
	MV_U32   BUS_INCTVTY_LMT:16;
#else
	MV_U32   BUS_INCTVTY_LMT:16;
	MV_U32   MAX_CONN_TM_LMT:16;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_PL_TIMER, *PREG_CMD_PL_TIMER;

/* CMD_PLL_PHY_CONFIG bits */
typedef struct _REG_CMD_PLL_PHY_CONFIG
{
#if __MV_BIG_ENDIAN_BITFIELD__
#else
	MV_U32   reg_phy_refdiv:2;
	MV_U32   reg_phy_fbdiv:7;
	MV_U32   phy_reg_en:1;
	MV_U32   Reserved:22;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_PLL_PHY_CONFIG, *PREG_CMD_PLL_PHY_CONFIG;

/* CMD_PHY_CONTROL bits */
typedef struct _REG_CMD_PHY_CONTROL
{
#if __MV_BIG_ENDIAN_BITFIELD__
#else
	MV_U32   o_lb_enable:1;
	MV_U32   o_lb_long_short:1;
	MV_U32   o_lb_start_rd:1;
	MV_U32   Reserved0:1;
	MV_U32   o_lb_rxsel:2;
	MV_U32   o_lb_txsel:2;
	MV_U32   o_lb_mode:4;
	MV_U32   Reserved1:1;
	MV_U32   i_phytest_pass:1;
	MV_U32   i_phytest_lock:1;
	MV_U32   Reserved2:17;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_PHY_CONTROL, *PREG_CMD_PHY_CONTROL;

/* CMD_APP_ERR_CONFIG bits */
typedef struct _REG_CMD_APP_ERR_CONFIG
{
#if __MV_BIG_ENDIAN_BITFIELD__
#else
	MV_U32   cmd_init_err:1;
	MV_U32   cmd_port_err:1;
	MV_U32   cmd_prtcl_err:1;
	MV_U32   cmd_fill_byte_err:1;
	MV_U32   cmd_no_space_err:1;
	MV_U32   rsps_init_bit_err:1;
	MV_U32   rsps_ssp_prtcl_err:1;
	MV_U32   rsps_port_err:1;
	MV_U32   rsps_underflow_err:1;
	MV_U32   rsps_tag_err:1;
	MV_U32   Reserved0:2;
	MV_U32   xrdy_init_err:1;
	MV_U32   xrdy_prtcl_err:1;
	MV_U32   xrdy_port_error:1;
	MV_U32   xrdy_offset_err:1;
	MV_U32   xrdy_tag_err:1;
	MV_U32   xrdy_overflow_err:1;
	MV_U32   xrdy_fill_byte_err:1;
	MV_U32   data_iu_init_err:1;
	MV_U32   data_iu_port_err:1;
	MV_U32   data_iu_tag_err:1;
	MV_U32   tgt_mode_data_iu_tag_err:1;
	MV_U32   data_offset_err:1;
	MV_U32   data_overflow_err:1;
	MV_U32   resps_iu_seq_err:1;
	MV_U32   Reserved1:1;
	MV_U32   data_iu_seq_err:1;
	MV_U32   Reserved2:4;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_APP_ERR_CONFIG, *PREG_CMD_APP_ERR_CONFIG;

/* CMD_PND_FIFO_CONTROL0 bits */
typedef struct _REG_CMD_PND_FIFO_CONTROL0
{
#if __MV_BIG_ENDIAN_BITFIELD__
#else
	MV_U32   lpf0_reset:1;
	MV_U32   hpf0_reset:1;
	MV_U32   dtf0_reset:1;
	MV_U32   lpf1_reset:1;
	MV_U32   hpf1_reset:1;
	MV_U32   dtf1_reset:1;
	MV_U32   lpf2_reset:1;
	MV_U32   hpf2_reset:1;
	MV_U32   dtf2_reset:1;
	MV_U32   lpf3_reset:1;
	MV_U32   hpf3_reset:1;
	MV_U32   dtf3_reset:1;
	MV_U32   tsf_rst:1;
	MV_U32   Reserved0:2;
	MV_U32   slot_transmit_rst:1;
	MV_U32   hpf0_pause:1;
	MV_U32   lpf0_pause:1;
	MV_U32   dtf0_pause:1;
	MV_U32   Reserved1:1;
	MV_U32   hpf1_pause:1;
	MV_U32   lpf1_pause:1;
	MV_U32   dtf1_pause:1;
	MV_U32   Reserved2:1;
	MV_U32   hpf2_pause:1;
	MV_U32   lpf2_pause:1;
	MV_U32   dtf2_pause:1;
	MV_U32   Reserved3:1;
	MV_U32   hpf3_pause:1;
	MV_U32   lpf3_pause:1;
	MV_U32   dtf3_pause:1;
	MV_U32   Reserved4:1;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_PND_FIFO_CONTROL0, *PREG_CMD_PND_FIFO_CONTROL0;

/* CMD_HOST_CONTROL bits */
typedef struct _REG_CMD_HOST_CONTROL
{
#if __MV_BIG_ENDIAN_BITFIELD__
#else
	MV_U32   host_addr:16;
	MV_U32   host_be:4;
	MV_U32   host_write:1;
	MV_U32   host_req:1;
	MV_U32   Reserved:10;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_HOST_CONTROL, *PREG_CMD_HOST_CONTROL;

/* CMD_PHY_MODE_21 bits */
typedef struct _REG_CMD_PHY_MODE_21
{
#if __MV_BIG_ENDIAN_BITFIELD__
#else
	MV_U32   v_chg_tmr:16;
	MV_U32   spd_chg_tmr:16;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_PHY_MODE_21, *PREG_CMD_PHY_MODE_21;

/* CMD_SL_MODE0 bits */
typedef struct _REG_CMD_SL_MODE0
{
#if __MV_BIG_ENDIAN_BITFIELD__
#else
	MV_U32   open_rejct_retry:7;
	MV_U32   Reserved0:5;
	MV_U32   stp_offset_chk_dis:1;
	MV_U32   stp_buf_siz:2;
	MV_U32   cn_rate_retry_dis:1;
	MV_U32   Reserved1:16;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_SL_MODE0, *PREG_CMD_SL_MODE0;

/* CMD_SL_MODE1 bits */
typedef struct _REG_CMD_SL_MODE1
{
#if __MV_BIG_ENDIAN_BITFIELD__
#else
	MV_U32   bcast_chg_det:8;
	MV_U32   unasc_fis_blk_stp_opn_en:1;
	MV_U32   bcast_stop_en:1;
	MV_U32   wd_to_stop_en:1;
	MV_U32   phyrdy_chg_stop_en:1;
	MV_U32   Reserved0:3;
	MV_U32   ssp_disc_data_en:1;
	MV_U32   Reserved1:16;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CMD_SL_MODE1, *PREG_CMD_SL_MODE1;

enum {
/* Port Config Registers PORT_CONFIG_ADDR, PORT_CONFIG_DATA */
	CONFIG_DEV_INFO          = 0x00, /* port device info register */
	CONFIG_DEV_ADDR_LO     = 0x04, /* Port device SAS addr lo register */
	CONFIG_DEV_ADDR_HI     = 0x08, /* Port device SAS addr hi register */
	CONFIG_ATT_DEV_INFO    = 0x0c, /* attached device info register */
	CONFIG_ATT_DEV_ADDR_LO = 0x10, /* attached device SAS addr lo reg */
	CONFIG_ATT_DEV_ADDR_HI = 0x14, /* attached device SAS addr hi reg */
	CONFIG_SATA_CONTROL    = 0x18, /* port SATA control register */
	CONFIG_PHY_STATUS      = 0x1c, /* port phy status register */
	CONFIG_SATA_SIG0       = 0x20, /* port SATA signature FIS(Byte 0-3) */
	CONFIG_SATA_SIG1       = 0x24, /* port SATA signature FIS(Byte 4-7) */
	CONFIG_SATA_SIG2       = 0x28, /* port SATA signature FIS(Byte 8-11) */
	CONFIG_SATA_SIG3       = 0x2c, /* port SATA signature FIS(Byte 12-15)*/
	CONFIG_R_ERR_COUNT     = 0x30, /* port R_ERR count register */
	CONFIG_CRC_ERR_COUNT   = 0x34, /* port CRC error count register */
	CONFIG_WIDE_PORT       = 0x38, /* port wide participating register */

        /* CONFIG_DEV_INFO/CONFIG_ATT_DEV_INFO (0x00) bits */
	PORT_DEV_TYPE_MASK     = (0x7 << 0),
	PORT_DEV_INIT_MASK     = (0x7 << 9),
	PORT_DEV_TRGT_MASK     = (0x7 << 17),
	PORT_DEV_STP_INIT      = (1 << 9),
	PORT_DEV_SMP_INIT      = (1 << 10),
	PORT_DEV_SSP_INIT      = (1 << 11),
	PORT_DEV_STP_TRGT      = (1 << 17),
	PORT_DEV_SMP_TRGT      = (1 << 18),
	PORT_DEV_SSP_TRGT      = (1 << 19),
	PORT_PHY_ID_MASK       = (0xFF << 24),
};

/* CONFIG_SATA_CONTROL bits */
typedef struct _REG_CONFIG_SATA_CONTROL
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   PM_CNTRL:2;      /* set */
	MV_U32   SRST:1;
	MV_U32   Reserved3:1;
	MV_U32   PMODE:2;      /* read */
	MV_U32   Reserved2:1;
	MV_U32   PORT_SEL:1;
	MV_U32   BIST_RSLT:1;
	MV_U32   DMAT_HONOR:1;
	MV_U32   SNGL_SYNC_EN:1;
	/* 0- no SRST */
	MV_U32   SRST_ENBL:1;      /* 1- send SYNC and soft reset, if SRST=1 */
	MV_U32   Reserved1:1;
	MV_U32   DMAT_TRNSFR:1;
	MV_U32   CONT_DSBL:1;
	MV_U32   TX_SCRMBL_DSBL:1;
	MV_U32   RX_SCRMBL_DSBL:1;
	MV_U32   CRC_CHK_DSBL:1;
	MV_U32   RX_CRC_REVERSE:1;
	MV_U32   XRDY:1;         /* send 0- SYNC, 1- R-ERR if non XRDY*/
	MV_U32   PMODE_ENBL:2;
	MV_U32   BIST_ENBL:1;
	MV_U32   BIST_DIR:1;      /* 0-RX BIST FIS, 1-TX BIST FIS*/
	MV_U32   BIST_MODE:8;
#else
	MV_U32   BIST_MODE:8;
	MV_U32   BIST_DIR:1;         /* 0-RX BIST FIS, 1-TX BIST FIS*/
	MV_U32   BIST_ENBL:1;
	MV_U32   PMODE_ENBL:2;
	MV_U32   XRDY:1;            /* send 0- SYNC, 1- R-ERR if non XRDY*/
	MV_U32   RX_CRC_REVERSE:1;
	MV_U32   CRC_CHK_DSBL:1;
	MV_U32   RX_SCRMBL_DSBL:1;
	MV_U32   TX_SCRMBL_DSBL:1;
	MV_U32   CONT_DSBL:1;
	MV_U32   DMAT_TRNSFR:1;
	MV_U32   Reserved1:1;
	MV_U32   SRST_ENBL:1;      /* 1- send SYNC and soft reset, if SRST=1 */
	/* 0- no SRST */
	MV_U32   SNGL_SYNC_EN:1;
	MV_U32   DMAT_HONOR:1;
	MV_U32   BIST_RSLT:1;
	MV_U32   PORT_SEL:1;
	MV_U32   Reserved2:1;
	MV_U32   PMODE:2;         /* read */
	MV_U32   Reserved3:1;
	MV_U32   SRST:1;
	MV_U32   PM_CNTRL:2;         /* set */
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */
} REG_CONFIG_SATA_CONTROL, *PREG_CONFIG_SATA_CONTROL;

/* Power Mode PM_CNTRL/PMODE */
#define PMODE_PARTIAL      0x10
#define PMODE_SLUMBER      0x01

/* CONFIG_PHY_STATUS bits */
typedef struct _REG_CONFIG_PHY_STATUS
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved2:13;
	MV_U32   TXIMP:4;
	MV_U32   RXIMP:4;
	MV_U32   PLL_CAL_DONE:1;
	MV_U32   PHY_PLL_LOCK:1;
	MV_U32   KVCO:3;
	MV_U32   IMP_CAL_DONE:1;
	MV_U32   NGTD_SPEED:1;
	MV_U32   Reserved1:1;
	MV_U32   PHY_RDY:1;
	MV_U32   DW_SYNC:1;   
	MV_U32   OOB_DTCTD:1;
#else
	MV_U32   OOB_DTCTD:1;
	MV_U32   DW_SYNC:1;   
	MV_U32   PHY_RDY:1;
	MV_U32   Reserved1:1;
	MV_U32   NGTD_SPEED:1;
	MV_U32   IMP_CAL_DONE:1;
	MV_U32   KVCO:3;
	MV_U32   PHY_PLL_LOCK:1;
	MV_U32   PLL_CAL_DONE:1;
	MV_U32   RXIMP:4;
	MV_U32   TXIMP:4;
	MV_U32   Reserved2:13;
#endif
} REG_CONFIG_PHY_STATUS, *PREG_CONFIG_PHY_STATUS;

/* CONFIG_R_ERR_COUNT/CONFIG_CRC_ERR_COUNT bits */
#define ERR_COUNT_MASK      0x0ffff

enum {
        /* CONFIG_WIDE_PORT (0x38) bits */
	WIDE_PORT_PHY_MASK  = (0xF << 0), /* phy map in a wide port */

/* XOR_PORT_REG */
	/* XOR port registers */
	XOR_CONTROL         = 0x504,/* xor port control/status register */
	XOR_LST_ADDR        = 0x508,/* xor port cmd list base addr low 32 */
	XOR_LST_ADDR_HI       = 0x50c,/* xor port cmd list base addr high 32 */
	XOR_DELV_Q_CONFIG   = 0x510,/* xor port delivery queue configuration */
	XOR_DELV_Q_ADDR     = 0x514,/* xor port delivery queue base addr */
	XOR_DELV_Q_ADDR_HI  = 0x518,/* xor port delivery queue base addr hi */
	XOR_DELV_Q_WR_PTR   = 0x51c,/* xor port delivery queue write pointer */
	XOR_DELV_Q_RD_PTR   = 0x520,/* xor port delivery queue read pointer */
	XOR_CMPL_Q_CONFIG   = 0x524,/* xor port cmpl queue configuration */
	XOR_CMPL_Q_ADDR     = 0x528,/* xor port cmpl queue base address */
	XOR_CMPL_Q_ADDR_HI  = 0x52c,/* xor port cmpl queue base address hi */
	XOR_CMPL_Q_WR_PTR   = 0x530,/* xor port cpml queue write pointer */
	XOR_CMPL_Q_RD_PTR   = 0x534,/* xor port cpml queue read pointer */
	XOR_COAL_CONFIG     = 0x538,/* xor port intr coalescing config */
	XOR_COAL_TIMEOUT    = 0x53c,/* xor port intr coalescing time wait */
	XOR_IRQ_STAT        = 0x540,/* xor port interrupt status */
	XOR_IRQ_MASK        = 0x544,/* xor port intr enable/disable mask */
	XOR_ERR_CODE        = 0x560,/* xor port error code register */
	XOR_ERR_TBL_ADDR    = 0x564,/* xor port error table base address */
	XOR_ERR_TBL_ADDR_HI = 0x568,/* xor port error table base address hi */
	XOR_ERR_OFFSET0       = 0x570,/* xor port B0 error offset */
	XOR_ERR_LEN0        = 0x574,/* xor port B0 error length */
	XOR_ERR_OFFSET1     = 0x578,/* xor port B1 error offset */
	XOR_ERR_LEN1        = 0x57c,/* xor port B1 error length */

        /* XOR_CONTROL (R504h) */
	XOR_ENABLE             = (1 << 0),
	XOR_RESET              = (1 << 1),
	ABORT_ZRC_ERROR        = (1 << 3), /* ZRC : Zero Result Check */
	PAUSE_AT_TABLE_BOUNDRY = (1 << 4),
	XOR_PAUSED             = (1 << 5),
	XOR_CMD_RUNNING        = (1 << 6), /* a mask ? - A.C. */
	XOR_CMD_CMPL_SELF_CLEAR = (1 << 7),
	XOR_CMD_CMPL_IRQ_MODE  = (1 << 7),
	CURRENT_CMD_SLOT_MASK  = (0xFFF << 16),

        /* XOR_DELV_Q_CONFIG (0x510) bits */
	XOR_DELV_QUEUE_SIZE_MASK   = (0xFFF << 0),
	XOR_DELV_QUEUE_ENABLE      = (1 << 16),
};

/* XOR_DELV_Q_WR_PTR bits */
typedef struct _REG_XOR_DELV_Q_WR_PTR
{
#if __MV_BIG_ENDIAN_BITFIELD__
	MV_U32   Reserved:20;
	MV_U32   DELV_QUEUE_WRT_PTR:12;
#else
	MV_U32   DELV_QUEUE_WRT_PTR:12;
	MV_U32   Reserved:20;
#endif /* __MV_BIG_ENDIAN_BITFIELD__ */