instruction_register.vhd

一个8位微处理器的VHDL代码以及testbench

library ieee;
use ieee.std_logic_1164.all; -- each module will need to use std_logic

entity instruction_register is
	port(   reset : in std_logic; -- master reset, same for each sequential module
	        clk :	in std_logic; -- same clock drives each sequential module
	        we:               in std_logic; -- controller sets this signal when Instruction_out need to be fetched	
	        IR_Code_in:          in std_logic_vector(13 downto 0); -- Code fetched from the Program Memory
	        Instruction_out:	     out std_logic_vector(13 downto 0);
	        address_out: out std_logic_vector(12 downto 0));
end entity instruction_register;

architecture instruction_register of instruction_register is
signal IR_Out: std_logic_vector(13 downto 0);
begin
	process(clk, reset) is
	begin
	   if (reset = '1') then
	      IR_Out <= (others => '0');
	      address_out <= (others => '0');
	   else
	      if rising_edge(clk) then
	         if (we = '1') then
	            IR_Out <= IR_Code_in;
	            address_out <= "00" & IR_Code_in (10 downto 0);
	         end if;
              end if;
           end if;
	end process; 
	Instruction_out <= IR_Out;
end;