port_k.vhd

来自「一个8位微处理器的VHDL代码以及testbench」· VHDL 代码 · 共 48 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity port_k is
	port( reset : in std_logic; 
	      clk :	in std_logic;
	      load_ddrk : in std_logic;
	      ddrk_in: in std_logic_vector(7 downto 0);
	    latch_in: in std_logic_vector(7 downto 0);
	    k_in: out std_logic_vector(7 downto 0);
	    k: inout std_logic_vector(7 downto 0);
	    k_latch: in std_logic);
end entity port_k;

architecture port_k of port_k is
signal k_out: std_logic_vector(7 downto 0);
signal out_en: std_logic_vector(7 downto 0);
begin
	process(k, k_out, out_en)
	begin
	   for i in 0 to 7 loop
	      k_in(i) <= k(i);      
	      if(out_en(i) = '1')then
	        k(i) <= k_out(i);
	      else
	        k(i) <= 'Z';
			end if;
		end loop;
	end process;
	

	process(clk,reset) is
	begin
	   if(reset = '1') then
	      out_en <= "00000000";
	      k_out <= (others => '0');
	   elsif rising_edge(clk) then
    		   if(load_ddrk = '1') then
    		       out_en <= ddrk_in;
   		   end if;
   		   if (k_latch = '1') then
   		       k_out <= latch_in;
   		   end if;
		end if;	
	end process; 
	
end architecture port_k;