program_counter.vhd

来自「一个8位微处理器的VHDL代码以及testbench」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all; -- each module will need to use std_logic
use ieee.numeric_std.all; -- program counter needs support for numerical operations
entity program_counter is
	port(   reset : in std_logic; -- master reset, same for each sequential module
	          clk :	in std_logic; -- same clock drives each sequential module
	          we:      in std_logic; -- controller sets this signal when PC is loaded with branch address
	          increment:      in std_logic; -- controller sets this when an increment is required
	          branch_address: in std_logic_vector(12 downto 0);
	          PCout:	           out std_logic_vector(12 downto 0) ); -- this is the next instr address
end entity program_counter;


architecture program_counter of program_counter is
signal PC_count: unsigned(12 downto 0);
begin
	process(clk) is
	begin
		if rising_edge(clk) then
			if (reset = '1') then PC_count <= (others => '0');
			elsif (we = '1') then PC_count <= unsigned(branch_address);
			elsif (increment = '1') then PC_count <= (PC_count + 1); 
			end if;
		end if; -- rising_edge(clk)
	
	end process; 
	PCout <= std_logic_vector(PC_count);
end;