ram.vhd

一个8位微处理器的VHDL代码以及testbench

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ram is
	port(clk :in std_logic;
		write_data: in std_logic_vector(7 downto 0);
	       address:    in std_logic_vector(4 downto 0);
		    read_data:  out std_logic_vector(7 downto 0);
    		    we:         in std_logic);
end entity ram;


architecture ram of ram is
type mem_type is array (0 to 31) of std_logic_vector(7 downto 0);
signal mem: mem_type;

begin
    read_data <= mem(conv_integer(unsigned(address)));
    
    process(clk)
        begin
        if(clk'event and clk = '1') then
            if (we = '1') then
                mem(conv_integer(unsigned(address))) <= write_data;
            end if;
        end if;
    end process;
end architecture ram;