cpu_testbench.vhd

一个8位微处理器的VHDL代码以及testbench

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.controller_const.all;
--use work.alu_const.all;
entity Test_CPU is
end entity Test_CPU;

architecture Test_CPU of Test_CPU is
	
	component CPU
	port (  clk,reset: in std_logic;
		portA: inout std_logic_vector(7 downto 0);
		portB: inout std_logic_vector(7 downto 0)
	);	    
	end component;

   signal clk: std_logic := '0';
   signal reset: std_logic;	
   signal portA: std_logic_vector (7 downto 0);
   signal portB: std_logic_vector (7 downto 0);
   
	begin

	CPU_0: CPU port map(clk, reset, portA, portB);
   clk <= NOT clk after 1 ms;
   reset <= '0', '1' after 5 ms, '0' after 10 ms;
   portA <= "ZZZZZZZZ";
   portB <= "ZZZZZZZZ";

end architecture Test_CPU;