work_register.vhd

一个8位微处理器的VHDL代码以及testbench

library ieee;
use ieee.std_logic_1164.all; -- each module will need to use std_logic

entity work_register is
	port(   reset : in std_logic; -- master reset, same for each sequential module
	        clk :	in std_logic; -- same clock drives each sequential module
	        we:               in std_logic; -- controller sets this signal when WR_out need to be fetched	
	        WR_Code_in:          in std_logic_vector(7 downto 0);
	        WR_out:	     out std_logic_vector(7 downto 0) ); 
end entity work_register;

architecture work_register of work_register is
signal WR_internal: std_logic_vector(7 downto 0);
begin
	process(clk) is
	begin
		if rising_edge(clk) then
			if (reset = '1') then WR_internal <= (others => '0');
			elsif (we = '1') then WR_internal <= WR_Code_in;
			end if;
		end if; -- rising_edge(clk)
	
	end process; 
	WR_out <= WR_internal;
end;