cpu.vhd

一个8位微处理器的VHDL代码以及testbench

library ieee;
use ieee.std_logic_1164.all;

entity CPU is
	port (	reset, clk: in std_logic;
		PortA: inout std_logic_vector(7 downto 0);
		PortB: inout std_logic_vector(7 downto 0));
end entity CPU;

architecture CPU of CPU is
   component work_register
   	port(	reset : in std_logic; 
   		clk : in std_logic; 
   	        we : in std_logic;
   	        WR_Code_in : in std_logic_vector(7 downto 0);
   	        WR_out : out std_logic_vector(7 downto 0)); 
   end component;


   component port_k
	port(	reset : in std_logic; 
		clk : in std_logic;
		load_ddrk : in std_logic;
		ddrk_in : in std_logic_vector(7 downto 0);
		latch_in : in std_logic_vector(7 downto 0);
		k_in : out std_logic_vector(7 downto 0);
		k : inout std_logic_vector(7 downto 0);
		k_latch : in std_logic);
   end component;


   component ram
	port(	clk: in std_logic;
	   write_data : in std_logic_vector(7 downto 0);
		address : in std_logic_vector(4 downto 0);
		read_data : out std_logic_vector(7 downto 0);
		we : in std_logic);
   end component;


   component program_memory
	port(	addr : in std_logic_vector(12 downto 0);
		data : out std_logic_vector(13 downto 0)); 
   end component;


   component alu
	port(	a, b : in std_logic_vector(7 downto 0);
		func : in std_logic_vector(3 downto 0);
		cin : in std_logic;
		cout, zero, ov : out std_logic;
		ALU_out : out std_logic_vector(7 downto 0);
      alu_bits: in std_logic_vector (2 downto 0));
   end component;

   component instruction_register
	port(	reset : in std_logic;
		clk : in std_logic;
		we : in std_logic;
		IR_Code_in : in std_logic_vector(13 downto 0);
		Instruction_out : out std_logic_vector(13 downto 0);
      address_out: out std_logic_vector(12 downto 0));
   end component;

   component program_counter
	port(	reset : in std_logic;
		clk :	in std_logic;
		we : in std_logic;
		increment : in std_logic;
		branch_address : in std_logic_vector(12 downto 0);
		PCout : out std_logic_vector(12 downto 0) );
   end component;

   component controller
    port ( reset	:	in std_logic;   -- master reset, same for each sequential module
       clk		:	in std_logic;   -- same clock drives each sequential module
       ram_data_out	:	in std_logic_vector(7 downto 0);
	    port_a_out	:	in std_logic_vector(7 downto 0);
	    port_b_out 	:	in std_logic_vector(7 downto 0);
	    address_out 	:	in std_logic_vector(7 downto 0);
       ir_out	:	in std_logic_vector(13 downto 0);
       wreg_we 	:	out std_logic;
       irreg_we	:	out std_logic;
       pc_we	:	out std_logic;
       pc_inc	:	out std_logic;
       ram_we	:	out std_logic;
       alu_func	:	out std_logic_vector(3 downto 0);
       alu_b	:	out std_logic_vector(7 downto 0); --MUX OUTPUT
       alu_bits: out std_logic_vector (2 downto 0);
       cout		:	in std_logic;
       zero		:	in std_logic;
       ov		:	in std_logic;
       port_latch_a	:	out std_logic;
	    port_latch_b	:	out std_logic;
	    load_ddr_a	:	out std_logic;
	    load_ddr_b	:	out std_logic;
	    ddr_a_in	:	out std_logic_vector (7 downto 0);
	    ddr_b_in	:	out std_logic_vector (7 downto 0));
   end component;



   signal instruction_pm_out: std_logic_vector(13 downto 0);
   signal instruction_ir_out: std_logic_vector(13 downto 0);
   signal address_pc_out : std_logic_vector(12 downto 0);
   signal address_ir_out : std_logic_vector(12 downto 0);
   signal workr_data_out : std_logic_vector(7 downto 0);
   signal ram_data_out   : std_logic_vector(7 downto 0);	
   signal alu_data_out   : std_logic_vector(7 downto 0);		   
   signal data_port_a_out: std_logic_vector(7 downto 0);	
   signal data_port_b_out: std_logic_vector(7 downto 0);			
   signal alu_b: std_logic_vector(7 downto 0);
   signal alu_bits: std_logic_vector(2 downto 0);		
   signal alu_function: std_logic_vector(3 downto 0);
   signal pc_increment: std_logic;	
   signal ir_enable: std_logic;
   signal pc_enable: std_logic;
   signal ram_enable: std_logic;	
   signal workr_enable: std_logic;
   signal load_ddr_a: std_logic;
   signal load_ddr_b: std_logic;  
   signal ddr_a_in: std_logic_vector(7 downto 0);	 
   signal ddr_b_in: std_logic_vector(7 downto 0);	 
   signal port_latch_a: std_logic;
   signal port_latch_b: std_logic;
   signal alu_cin: std_logic;
   signal alu_c_out: std_logic;
   signal alu_z_out: std_logic;
   signal alu_v_out: std_logic;

begin

   work_register_0: work_register port map(reset, clk, workr_enable, alu_data_out, workr_data_out);
   alu_0: alu port map(workr_data_out, alu_b, alu_function, alu_cin, alu_c_out, alu_z_out, alu_v_out, alu_data_out, alu_bits);
   port_a: port_k port map(reset, clk, load_ddr_a, workr_data_out, alu_data_out, data_port_a_out, PortA, port_latch_a);
   port_b: port_k port map(reset, clk, load_ddr_b, workr_data_out, alu_data_out, data_port_b_out, PortB, port_latch_b);		
   program_counter_0: program_counter port map(reset, clk, pc_enable, pc_increment, address_ir_out, address_pc_out);
   instruction_register_0: instruction_register port map(reset, clk, ir_enable, instruction_pm_out, instruction_ir_out, address_ir_out);
   program_memory_0: program_memory port map(address_pc_out, instruction_pm_out);
   ram_0: ram port map(clk, alu_data_out, address_ir_out(4 downto 0), ram_data_out, ram_enable);
   controller_0: controller port map(reset, clk, ram_data_out, data_port_a_out, data_port_b_out, instruction_ir_out(7 downto 0) ,instruction_ir_out, workr_enable, ir_enable, pc_enable, pc_increment, ram_enable, alu_function, alu_b, alu_bits, alu_c_out, alu_z_out, alu_v_out, port_latch_a, port_latch_b, load_ddr_a, load_ddr_b, ddr_a_in, ddr_b_in);
end architecture CPU;