📄 controller.vhd
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alu_b <= port_a_out; port_latch_a <= '1'; elsif (k7 = "0000110") then -- PortB (address 6) alu_b <= port_b_out; port_latch_b <= '1'; else -- RAM alu_b <= ram_data_out; ram_we <= '1'; end if; else wreg_we <= '1'; if(k7 = "0000101") then -- PortA (address 5) alu_b <= port_a_out; elsif (k7 = "0000110") then -- PortB (address 6) alu_b <= port_b_out; else -- RAM alu_b <= ram_data_out; end if; end if; when DECFSZ => alu_func <= alu_dec; if (zero = '1') then pc_inc <= '1'; end if; if (d='1') then wreg_we <= '0'; if(k7 = "0000101") then -- PortA (address 5) alu_b <= port_a_out; port_latch_a <= '1'; elsif (k7 = "0000110") then -- PortB (address 6) alu_b <= port_b_out; port_latch_b <= '1'; else -- RAM alu_b <= ram_data_out; ram_we <= '1'; end if; else wreg_we <= '1'; if(k7 = "0000101") then -- PortA (address 5) alu_b <= port_a_out; elsif (k7 = "0000110") then -- PortB (address 6) alu_b <= port_b_out; else -- RAM alu_b <= ram_data_out; end if; end if; when INCF => alu_func <= alu_inc; if (d='1') then wreg_we <= '0'; if(k7 = "0000101") then -- PortA (address 5) alu_b <= port_a_out; port_latch_a <= '1'; elsif (k7 = "0000110") then -- PortB (address 6) alu_b <= port_b_out; port_latch_b <= '1'; else -- RAM alu_b <= ram_data_out; ram_we <= '1'; end if; else wreg_we <= '1'; if(k7 = "0000101") then -- PortA (address 5) alu_b <= port_a_out; elsif (k7 = "0000110") then -- PortB (address 6) alu_b <= port_b_out; else -- RAM alu_b <= ram_data_out; end if; end if; when MOVF => alu_func <= alu_pass_b; if (d='1') then wreg_we <= '0'; if(k7 = "0000101") then -- PortA (address 5) alu_b <= port_a_out; port_latch_a <= '1'; elsif (k7 = "0000110") then -- PortB (address 6) alu_b <= port_b_out; port_latch_b <= '1'; else -- RAM alu_b <= ram_data_out; ram_we <= '1'; end if; else wreg_we <= '1'; if(k7 = "0000101") then -- PortA (address 5) alu_b <= port_a_out; elsif (k7 = "0000110") then -- PortB (address 6) alu_b <= port_b_out; else -- RAM alu_b <= ram_data_out; end if; end if; when MOVLW => alu_func <= alu_pass_b; alu_b <= address_out; wreg_we <= '1'; when SUBLW => alu_func <= alu_sub; wreg_we <= '1'; alu_b <= address_out; when SUBWF => alu_func <= alu_sub; if (d='1') then wreg_we <= '0'; if(k7 = "0000101") then -- PortA (address 5) alu_b <= port_a_out; port_latch_a <= '1'; elsif (k7 = "0000110") then -- PortB (address 6) alu_b <= port_b_out; port_latch_b <= '1'; else -- RAM alu_b <= ram_data_out; ram_we <= '1'; end if; else wreg_we <= '1'; if(k7 = "0000101") then -- PortA (address 5) alu_b <= port_a_out; elsif (k7 = "0000110") then -- PortB (address 6) alu_b <= port_b_out; else -- RAM alu_b <= ram_data_out; end if; end if; when XORLW => alu_func <= alu_xor; wreg_we <= '1'; alu_b <= address_out; when XORWF => alu_func <= alu_xor; if (d='1') then wreg_we <= '0'; if(k7 = "0000101") then -- PortA (address 5) alu_b <= port_a_out; port_latch_a <= '1'; elsif (k7 = "0000110") then -- PortB (address 6) alu_b <= port_b_out; port_latch_b <= '1'; else -- RAM alu_b <= ram_data_out; ram_we <= '1'; end if; else wreg_we <= '1'; if(k7 = "0000101") then -- PortA (address 5) alu_b <= port_a_out; elsif (k7 = "0000110") then -- PortB (address 6) alu_b <= port_b_out; else -- RAM alu_b <= ram_data_out; end if; end if; when IORLW => alu_func <= alu_or; wreg_we <= '1'; alu_b <= address_out; when others => case opcode4 is when BTFSS => alu_func <= alu_bit_test; alu_bits <= b; if(k7 = "0000101") then -- PortA (address 5) alu_b <= port_a_out; elsif (k7 = "0000110") then -- PortB (address 6) alu_b <= port_b_out; else -- RAM alu_b <= ram_data_out; end if; if (zero = '0') then pc_inc <= '1'; end if; when others => end case; end case; end case; end case; next_state <= ID; end case; end process comb;end architecture statemachine;
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