controller.vhd

一个8位微处理器的VHDL代码以及testbench

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.alu_const.all;
use work.controller_const.all;

entity controller is
    port ( reset	:	in std_logic;   -- master reset, same for each sequential module
           clk		:	in std_logic;   -- same clock drives each sequential module
	   ram_data_out	:	in std_logic_vector(7 downto 0);
	   port_a_out	:	in std_logic_vector(7 downto 0);
	   port_b_out 	:	in std_logic_vector(7 downto 0);
	   address_out 	:	in std_logic_vector(7 downto 0);
           ir_out	:	in std_logic_vector(13 downto 0);
           wreg_we 	:	out std_logic;
           irreg_we	:	out std_logic;
           pc_we	:	out std_logic;
           pc_inc	:	out std_logic;
           ram_we	:	out std_logic;
           alu_func	:	out std_logic_vector(3 downto 0);
           alu_b	:	out std_logic_vector(7 downto 0);
           alu_bits : out std_logic_vector(2 downto 0);
           cout		:	in std_logic;
           zero		:	in std_logic;
           ov		:	in std_logic;
           port_latch_a	:	out std_logic;
	   port_latch_b	:	out std_logic;
	   load_ddr_a	:	out std_logic;
	   load_ddr_b	:	out std_logic;
	   ddr_a_in	:	out std_logic_vector (7 downto 0);
	   ddr_b_in	:	out std_logic_vector (7 downto 0)
);
end entity controller;


architecture statemachine of controller is
    signal present_state, next_state : state;
    alias opcode11: std_logic_vector (10 downto 0) is ir_out (13 downto 3);
    alias opcode7 : std_logic_vector (6 downto 0) is ir_out (13 downto 7);
    alias opcode6 : std_logic_vector (5 downto 0) is ir_out (13 downto 8);
    alias opcode4 : std_logic_vector (3 downto 0) is ir_out (13 downto 10);
    alias opcode3 : std_logic_vector (2 downto 0) is ir_out (13 downto 11);
    alias opcode2 : std_logic_vector (1 downto 0) is ir_out (13 downto 12);
    alias k11     : std_logic_vector (10 downto 0) is ir_out (10 downto 0);
    alias k8      : std_logic_vector (7 downto 0) is ir_out (7 downto 0);
    alias k7      : std_logic_vector (6 downto 0) is ir_out (6 downto 0);
    alias b       : std_logic_vector (2 downto 0) is ir_out (9 downto 7);
    alias d       : std_logic is ir_out (7);


    begin
        seq: process(clk)
        begin
            if clk'event and clk = '1' then
                if  reset = '1' then
                    present_state <= STATE_RESET;
                else
                    present_state <= next_state;
                end if;
            end if;
        end process seq;

        comb: process (present_state, ir_out,ram_data_out,port_a_out,port_b_out,address_out,cout,zero,ov) is
        begin
        alu_func <= ALU_pass_z;            
        alu_b <= (others => '0');
        alu_bits <= "000";
        pc_inc <= '0';
        pc_we <= '0';
        wreg_we <= '0';
        irreg_we <= '0';
        ram_we <= '0';
        port_latch_a <= '0';
        port_latch_b <= '0';
        load_ddr_a <= '0';
        load_ddr_b <= '0';
        ddr_a_in <= "00000000";
        ddr_b_in <= "00000000";

        case present_state is
            when STATE_RESET =>
               alu_func <= ALU_pass_z;
               alu_b <= (others => '0');
               alu_bits <= "000";
               pc_inc <= '0';
               pc_we <= '0';
               wreg_we <= '0';
               irreg_we <= '0';
               ram_we <= '0';
               port_latch_a <= '0';
               port_latch_b <= '0';
               load_ddr_a <= '0';
               load_ddr_b <= '0';
               ddr_a_in <= "00000000";
               ddr_b_in <= "00000000";
            next_state <= ID;    
                
            when ID =>
                     case opcode3 is
                        when GOTO =>
                           pc_we <= '1';    -- Set PC WE to 1, select branch address
                        when others =>
                    	   pc_inc <= '1';
                     end case;
                     irreg_we <= '1';        
            next_state <= EXE;
         when EXE =>
            pc_inc <= '0';
            pc_we <= '0';
            irreg_we <= '0';
            case opcode11 is
                when TRIS =>
                    alu_func <= alu_pass_a;
                    if (ir_out(2 downto 0) = "101") then
                       load_ddr_a <= '1';
                    elsif (ir_out(2 downto 0) = "110") then
                       load_ddr_b <= '1';
                    end if;
                when others =>    
                case opcode7 is
                    when NOP =>
                       alu_func <= ALU_pass_z;
                       alu_b <= (others => '0');
                       pc_inc <= '0';
                       pc_we <= '0';
                       wreg_we <= '0';
                       irreg_we <= '0';
                       ram_we <= '0';
                       port_latch_a <= '0';
                       port_latch_b <= '0';
                       load_ddr_a <= '0';
                       load_ddr_b <= '0';
                       ddr_a_in <= "00000000";
                       ddr_b_in <= "00000000";
                    when MOVWF =>
		                  alu_func <= alu_pass_a;
                        wreg_we <= '0';
		                  if (k7 = "0000101") then     -- PortA (address 5)
                           port_latch_a <= '1';
                           port_latch_b <= '0';
                        elsif (k7 = "0000110") then  -- PortB (address 6)
                           port_latch_a <= '0';
                           port_latch_b <= '1';
                        else -- RAM
                           ram_we <= '1';
                        end if;                         
                    when others =>
                    case opcode6 is
                        when ADDLW =>
                            alu_func <= alu_add;
                           	wreg_we <= '1';
                      			   alu_b <= address_out;
                        when ADDWF =>
                            alu_func <= alu_add;                            
                            if (d='1') then
                               wreg_we <= '0';
                               if(k7 = "0000101") then     -- PortA (address 5)
                                  alu_b <= port_a_out;
                                  port_latch_a <= '1';
                               elsif (k7 = "0000110") then  -- PortB (address 6)
                                  alu_b <= port_b_out;
                                  port_latch_b <= '1';
                               else -- RAM
                                  alu_b <= ram_data_out;
       		                         ram_we <= '1';
                               end if;
                            else
                               wreg_we <= '1';
            		                 if(k7 = "0000101") then     -- PortA (address 5)
                                  alu_b <= port_a_out;
                               elsif (k7 = "0000110") then  -- PortB (address 6)
                                  alu_b <= port_b_out;
                               else -- RAM
                                  alu_b <= ram_data_out;
                               end if;
 			                   end if; 
                        when ANDLW =>
                            alu_func <= alu_and;
                            wreg_we <= '1';
                            alu_b <= address_out;
                        when ANDWF =>
                            alu_func <= alu_and;                            
                            if (d='1') then
                               wreg_we <= '0';
                               if(k7 = "0000101") then     -- PortA (address 5)