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Project Navigator Auto-Make Log File-------------------------------------
Started process "Compile HDL Simulation Libraries".Process "Compile HDL Simulation Libraries" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "IDE_EXT.v"ERROR:HDLCompilers:28 - IDE_EXT.v line 14 'A' has not been declaredModule <IDE_EXT> compiledAnalysis of file <IDE_EXT.prj> failed.--> Total memory usage is 48632 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "IDE_EXT.v"Module <IDE_EXT> compiledNo errors in compilationAnalysis of file <IDE_EXT.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <IDE_EXT>.Module <IDE_EXT> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <IDE_EXT>. Related source file is IDE_EXT.v.WARNING:Xst:1306 - Output <IDE_IORDY> is never assigned.WARNING:Xst:1306 - Output <IDE_CS0> is never assigned.WARNING:Xst:1306 - Output <IDE_CS1> is never assigned.WARNING:Xst:647 - Input <ADDR<4:3>> is never used.WARNING:Xst:1306 - Output <IDE_RST> is never assigned.WARNING:Xst:647 - Input <NRD> is never used.WARNING:Xst:647 - Input <NCS2> is never used.WARNING:Xst:647 - Input <NCS3> is never used.WARNING:Xst:647 - Input <NCS4> is never used.WARNING:Xst:647 - Input <NWE> is never used.WARNING:Xst:647 - Input <NRST> is never used.WARNING:Xst:1306 - Output <BUF_DIR> is never assigned.WARNING:Xst:1306 - Output <IDE_INT> is never assigned.WARNING:Xst:1306 - Output <IDE_IOR> is never assigned.WARNING:Xst:1306 - Output <IDE_IOW> is never assigned.WARNING:Xst:1306 - Output <BUF_OE> is never assigned.Unit <IDE_EXT> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <IDE_EXT> ...Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "IDE_EXT.v"ERROR:HDLCompilers:28 - IDE_EXT.v line 24 'IRQ0' has not been declaredModule <IDE_EXT> compiledAnalysis of file <IDE_EXT.prj> failed.--> Total memory usage is 48404 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "IDE_EXT.v"ERROR:HDLCompilers:28 - IDE_EXT.v line 25 'IRQ0' has not been declaredModule <IDE_EXT> compiledAnalysis of file <IDE_EXT.prj> failed.--> Total memory usage is 48404 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "IDE_EXT.v"Module <IDE_EXT> compiledNo errors in compilationAnalysis of file <IDE_EXT.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <IDE_EXT>.Module <IDE_EXT> is correct for synthesis. Set property "resynthesize = true" for unit <IDE_EXT>.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <IDE_EXT>. Related source file is IDE_EXT.v.WARNING:Xst:1306 - Output <IRQ<2:1>> is never assigned.WARNING:Xst:1305 - Output <IRQ<0>> is never assigned. Tied to value 0.WARNING:Xst:1305 - Output <IDE_IORDY> is never assigned. Tied to value 0.WARNING:Xst:647 - Input <NCS3> is never used.WARNING:Xst:647 - Input <NCS4> is never used.Unit <IDE_EXT> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <IDE_EXT> ...Completed process "Synthesize".
Started process "Translate".Extracting independent architecture files...Release 6.3i - ngdbuild G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -i -p xc9500xl IDE_EXT.ngc IDE_EXT.ngd Reading NGO file "e:/at91rm9200调研/pld_src/ide_ext/IDE_EXT.ngc" ...Reading component libraries for design expansion...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 38056 kilobytesWriting NGD file "IDE_EXT.ngd" ...Writing NGDBUILD log file "IDE_EXT.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 6.3i - CPLD Optimizer/Partitioner G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.WARNING:Cpld:1007 - Removing unused input(s) 'NCS3'. The input(s) are unused after optimization. Please verify functionality via simulation.WARNING:Cpld:1007 - Removing unused input(s) 'NCS4'. The input(s) are unused after optimization. Please verify functionality via simulation.Considering device XC9572XL-10-VQ64.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 14 equations into 4 function blocks................................................................................................字符转换错误：“Unconvertible UTF-8 character beginning with 0xb5”（行号可能太小）。line number 1Entity nullFailed to open: IDE_EXT_build.xmlDesign IDE_EXT has been optimized and fit into device XC9572XL-10-VQ64.Completed process "Fit".
Started process "Generate Programming File".Release 6.3i - Programming File Generator G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Generate Programming File".
Started process "Generate HTML report".Release 6.3i - CPLD HTML Report Processor G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.字符转换错误：“Unconvertible UTF-8 character beginning with 0xb5”（行号可能太小）。line number 1Entity nullFailed to open: IDE_EXT_build.xmlERROR:Cpld:1137 - Child process failed -mode 1
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "IDE_EXT.v"Module <IDE_EXT> compiledNo errors in compilationAnalysis of file <IDE_EXT.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <IDE_EXT>.ERROR:Xst:871 - IDE_EXT.v line 26: Invalid use of input signal <IDE_INT> as target. Set property "resynthesize = true" for unit <IDE_EXT>. Found 1 error(s). Aborting synthesis.--> Total memory usage is 48404 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "IDE_EXT.v"Module <IDE_EXT> compiledNo errors in compilationAnalysis of file <IDE_EXT.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <IDE_EXT>.Module <IDE_EXT> is correct for synthesis. Set property "resynthesize = true" for unit <IDE_EXT>.=========================================================================* HDL Synthesis *=========================================================================⌨️ 快捷键说明
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