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Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <IDE_EXT> ...Completed process "Synthesize".
Started process "Translate".Release 6.3i - ngdbuild G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -i -p xc9500xl IDE_EXT.ngc IDE_EXT.ngd Reading NGO file "e:/at91rm9200调研/pld_src/ide_ext/IDE_EXT.ngc" ...Reading component libraries for design expansion...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 38056 kilobytesWriting NGD file "IDE_EXT.ngd" ...Writing NGDBUILD log file "IDE_EXT.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 6.3i - CPLD Optimizer/Partitioner G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.WARNING:Cpld:1007 - Removing unused input(s) 'NCS4'. The input(s) are unused after optimization. Please verify functionality via simulation.Considering device XC9572XL-10-VQ64.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 21 equations into 4 function blocks............字符转换错误：“Unconvertible UTF-8 character beginning with 0xb5”（行号可能太小）。line number 1Entity nullFailed to open: IDE_EXT_build.xmlDesign IDE_EXT has been optimized and fit into device XC9572XL-10-VQ64.Completed process "Fit".
Started process "Generate Programming File".Release 6.3i - Programming File Generator G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Generate Programming File".
Started process "Generate HTML report".Release 6.3i - CPLD HTML Report Processor G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.字符转换错误：“Unconvertible UTF-8 character beginning with 0xb5”（行号可能太小）。line number 1Entity nullFailed to open: IDE_EXT_build.xmlERROR:Cpld:1137 - Child process failed -mode 1
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "IDE_EXT.v"ERROR:HDLCompilers:207 - IDE_EXT.v line 8 Signal 'ADDR' is not referenced in the module port listERROR:HDLCompilers:28 - IDE_EXT.v line 25 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 26 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 27 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 39 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 40 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 41 'ADDR' has not been declaredERROR:HDLCompilers:208 - IDE_EXT.v line 1 Port reference 'ADDR2' was not declared as input, inout or outputERROR:HDLCompilers:208 - IDE_EXT.v line 1 Port reference 'ADDR3' was not declared as input, inout or outputERROR:HDLCompilers:208 - IDE_EXT.v line 1 Port reference 'ADDR4' was not declared as input, inout or outputERROR:HDLCompilers:208 - IDE_EXT.v line 1 Port reference 'ADDR5' was not declared as input, inout or outputERROR:HDLCompilers:208 - IDE_EXT.v line 1 Port reference 'ADDR6' was not declared as input, inout or outputModule <IDE_EXT> compiledAnalysis of file <IDE_EXT.prj> failed.--> Total memory usage is 47984 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "IDE_EXT.v"ERROR:HDLCompilers:207 - IDE_EXT.v line 8 Signal 'ADDR' is not referenced in the module port listERROR:HDLCompilers:28 - IDE_EXT.v line 25 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 26 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 27 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 39 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 40 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 41 'ADDR' has not been declaredERROR:HDLCompilers:208 - IDE_EXT.v line 1 Port reference 'ADDR2' was not declared as input, inout or outputERROR:HDLCompilers:208 - IDE_EXT.v line 1 Port reference 'ADDR3' was not declared as input, inout or outputERROR:HDLCompilers:208 - IDE_EXT.v line 1 Port reference 'ADDR4' was not declared as input, inout or outputERROR:HDLCompilers:208 - IDE_EXT.v line 1 Port reference 'ADDR5' was not declared as input, inout or outputERROR:HDLCompilers:208 - IDE_EXT.v line 1 Port reference 'ADDR6' was not declared as input, inout or outputModule <IDE_EXT> compiledAnalysis of file <IDE_EXT.prj> failed.--> Total memory usage is 47756 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "IDE_EXT.v"ERROR:HDLCompilers:207 - IDE_EXT.v line 8 Signal 'ADDR' is not referenced in the module port listERROR:HDLCompilers:28 - IDE_EXT.v line 25 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 26 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 27 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 39 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 40 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 41 'ADDR' has not been declaredERROR:HDLCompilers:208 - IDE_EXT.v line 1 Port reference 'ADDR2' was not declared as input, inout or outputERROR:HDLCompilers:208 - IDE_EXT.v line 1 Port reference 'ADDR3' was not declared as input, inout or outputERROR:HDLCompilers:208 - IDE_EXT.v line 1 Port reference 'ADDR4' was not declared as input, inout or outputERROR:HDLCompilers:208 - IDE_EXT.v line 1 Port reference 'ADDR5' was not declared as input, inout or outputERROR:HDLCompilers:208 - IDE_EXT.v line 1 Port reference 'ADDR6' was not declared as input, inout or outputModule <IDE_EXT> compiledAnalysis of file <IDE_EXT.prj> failed.--> Total memory usage is 47756 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "IDE_EXT.v"ERROR:HDLCompilers:28 - IDE_EXT.v line 39 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 40 'ADDR' has not been declaredERROR:HDLCompilers:28 - IDE_EXT.v line 41 'ADDR' has not been declaredModule <IDE_EXT> compiledAnalysis of file <IDE_EXT.prj> failed.--> Total memory usage is 47756 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "IDE_EXT.v"Module <IDE_EXT> compiledNo errors in compilationAnalysis of file <IDE_EXT.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <IDE_EXT>.Module <IDE_EXT> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <IDE_EXT>. Related source file is IDE_EXT.v.WARNING:Xst:1306 - Output <SPCK> is never assigned.WARNING:Xst:1306 - Output <TIOA1> is never assigned.WARNING:Xst:1306 - Output <NPCS0> is never assigned.WARNING:Xst:1306 - Output <TWD> is never assigned.WARNING:Xst:647 - Input <NCS4> is never used.WARNING:Xst:1306 - Output <MOSI> is never assigned.WARNING:Xst:1306 - Output <PCK1> is never assigned.WARNING:Xst:1306 - Output <TWCK> is never assigned.WARNING:Xst:1306 - Output <MISO> is never assigned.Unit <IDE_EXT> synthesized.=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Advanced HDL Synthesis *==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <IDE_EXT> ...Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "IDE_EXT.v"Module <IDE_EXT> compiledNo errors in compilationAnalysis of file <IDE_EXT.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <IDE_EXT>.Module <IDE_EXT> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <IDE_EXT>. Related source file is IDE_EXT.v.WARNING:Xst:1306 - Output <SPCK> is never assigned.WARNING:Xst:1306 - Output <TIOA1> is never assigned.WARNING:Xst:1306 - Output <NPCS0> is never assigned.WARNING:Xst:1306 - Output <TWD> is never assigned.WARNING:Xst:647 - Input <NCS4> is never used.WARNING:Xst:1306 - Output <MOSI> is never assigned.WARNING:Xst:1306 - Output <PCK1> is never assigned.WARNING:Xst:1306 - Output <TWCK> is never assigned.WARNING:Xst:1306 - Output <MISO> is never assigned.Unit <IDE_EXT> synthesized.=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Advanced HDL Synthesis *==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <IDE_EXT> ...Completed process "Synthesize".
Started process "Translate".Release 6.1.03i - ngdbuild G.26Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc IDE_EXT.ucf -p xc9500xl IDE_EXT.ngcIDE_EXT.ngd Reading NGO file "E:/AT91RM9200调研/PLD_SRC/IDE_EXT/IDE_EXT.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "IDE_EXT.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0⌨️ 快捷键说明
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