__projnav.log

来自「非常优秀的CPLD源代码」· LOG 代码 · 共 1,813 行 · 第 1/5 页

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Started process "Translate".Release 6.1.03i - ngdbuild G.26Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -dd _ngo -uc IDE_EXT.ucf -p xc9500xl IDE_EXT.ngcIDE_EXT.ngd Reading NGO file "E:/AT91RM9200调研/PLD_SRC/IDE_EXT/IDE_EXT.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "IDE_EXT.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Total memory usage is 39708 kilobytesWriting NGD file "IDE_EXT.ngd" ...Writing NGDBUILD log file "IDE_EXT.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 6.1i - CPLD Optimizer/Partitioner G.26Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.WARNING:Cpld:1007 - Removing unused input(s) 'DATA<0>'.  The input(s) are unused   after optimization. Please verify functionality via simulation.WARNING:Cpld:1007 - Removing unused input(s) 'DATA<1>'.  The input(s) are unused   after optimization. Please verify functionality via simulation.WARNING:Cpld:1007 - Removing unused input(s) 'DATA<2>'.  The input(s) are unused   after optimization. Please verify functionality via simulation.WARNING:Cpld:1007 - Removing unused input(s) 'DATA<3>'.  The input(s) are unused   after optimization. Please verify functionality via simulation.WARNING:Cpld:1007 - Removing unused input(s) 'DATA<4>'.  The input(s) are unused   after optimization. Please verify functionality via simulation.WARNING:Cpld:1007 - Removing unused input(s) 'DATA<5>'.  The input(s) are unused   after optimization. Please verify functionality via simulation.WARNING:Cpld:1007 - Removing unused input(s) 'DATA<6>'.  The input(s) are unused   after optimization. Please verify functionality via simulation.WARNING:Cpld:1007 - Removing unused input(s) 'DATA<7>'.  The input(s) are unused   after optimization. Please verify functionality via simulation.Considering device XC9572XL-10-VQ64.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 21 equations into 4 function blocksDesign IDE_EXT has been optimized and fit into device XC9572XL-10-VQ64.Completed process "Fit".
Started process "Generate Programming File".Release 6.1i - Programming File Generator G.26Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Completed process "Generate Programming File".
Started process "Generate Timing".Release 6.1i - Timing Report Generator G.26Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Path tracing .....The number of paths traced: 28.The number of paths traced: 57.Generating performance summary ...IDE_EXT.tim has been created.Generating Stamp model files IDE_EXT.mod, IDE_EXT.data ...IDE_EXT.mod has been created.IDE_EXT.data has been created.Completed process "Generate Timing".



Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "IDE_EXT.v"Module <IDE_EXT> compiledNo errors in compilationAnalysis of file <IDE_EXT.prj> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <IDE_EXT>.Module <IDE_EXT> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <IDE_EXT>.    Related source file is IDE_EXT.v.WARNING:Xst:1306 - Output <SPCK> is never assigned.WARNING:Xst:1306 - Output <TIOA1> is never assigned.WARNING:Xst:1306 - Output <NPCS0> is never assigned.WARNING:Xst:1306 - Output <TWD> is never assigned.WARNING:Xst:1306 - Output <MOSI> is never assigned.WARNING:Xst:1306 - Output <PCK1> is never assigned.WARNING:Xst:1306 - Output <TWCK> is never assigned.WARNING:Xst:1306 - Output <MISO> is never assigned.WARNING:Xst:1777 - Inout <DATA> is never used or assigned.Unit <IDE_EXT> synthesized.=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================*                       Advanced HDL Synthesis                          *==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <IDE_EXT> ...Completed process "Synthesize".
Started process "Translate".Release 6.1.03i - ngdbuild G.26Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -dd _ngo -uc IDE_EXT.ucf -p xc9500xl IDE_EXT.ngcIDE_EXT.ngd Reading NGO file "E:/AT91RM9200调研/PLD_SRC/IDE_EXT/IDE_EXT.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "IDE_EXT.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Total memory usage is 39708 kilobytesWriting NGD file "IDE_EXT.ngd" ...Writing NGDBUILD log file "IDE_EXT.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 6.1i - CPLD Optimizer/Partitioner G.26Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.WARNING:Cpld:1007 - Removing unused input(s) 'DATA<0>'.  The input(s) are unused   after optimization. Please verify functionality via simulation.WARNING:Cpld:1007 - Removing unused input(s) 'DATA<1>'.  The input(s) are unused   after optimization. Please verify functionality via simulation.WARNING:Cpld:1007 - Removing unused input(s) 'DATA<2>'.  The input(s) are unused   after optimization. Please verify functionality via simulation.WARNING:Cpld:1007 - Removing unused input(s) 'DATA<3>'.  The input(s) are unused   after optimization. Please verify functionality via simulation.WARNING:Cpld:1007 - Removing unused input(s) 'DATA<4>'.  The input(s) are unused   after optimization. Please verify functionality via simulation.WARNING:Cpld:1007 - Removing unused input(s) 'DATA<5>'.  The input(s) are unused   after optimization. Please verify functionality via simulation.WARNING:Cpld:1007 - Removing unused input(s) 'DATA<6>'.  The input(s) are unused   after optimization. Please verify functionality via simulation.WARNING:Cpld:1007 - Removing unused input(s) 'DATA<7>'.  The input(s) are unused   after optimization. Please verify functionality via simulation.Considering device XC9572XL-10-VQ64.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 21 equations into 4 function blocksDesign IDE_EXT has been optimized and fit into device XC9572XL-10-VQ64.Completed process "Fit".
Started process "Generate Programming File".Release 6.1i - Programming File Generator G.26Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Completed process "Generate Programming File".
Started process "Generate Timing".Release 6.1i - Timing Report Generator G.26Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Path tracing .....The number of paths traced: 28.The number of paths traced: 57.Generating performance summary ...IDE_EXT.tim has been created.Generating Stamp model files IDE_EXT.mod, IDE_EXT.data ...IDE_EXT.mod has been created.IDE_EXT.data has been created.Completed process "Generate Timing".



Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "IDE_EXT.v"Module <IDE_EXT> compiledNo errors in compilationAnalysis of file <IDE_EXT.prj> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <IDE_EXT>.Module <IDE_EXT> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <IDE_EXT>.    Related source file is IDE_EXT.v.WARNING:Xst:1305 - Output <SPCK> is never assigned. Tied to value 0.WARNING:Xst:1305 - Output <TIOA1> is never assigned. Tied to value 0.WARNING:Xst:1305 - Output <NPCS0> is never assigned. Tied to value 0.WARNING:Xst:1305 - Output <TWD> is never assigned. Tied to value 0.WARNING:Xst:1305 - Output <PCK1> is never assigned. Tied to value 0.WARNING:Xst:1305 - Output <TWCK> is never assigned. Tied to value 0.WARNING:Xst:1306 - Output <MISO> is never assigned.WARNING:Xst:1777 - Inout <DATA> is never used or assigned.Unit <IDE_EXT> synthesized.=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================*                       Advanced HDL Synthesis                          *==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================WARNING:Xst:528 - Multi-source in Unit <IDE_EXT> on signal <MOSI> not replaced by logicSources are: MOSI5:MOSI, MOSI4:MOSI, MOSI3:MOSI, MOSI2:MOSI, MOSI1:MOSI, MOSI:MOSISignal is stuck at GNDERROR:Xst:415 - Synthesis failedCPU : 1.52 / 2.59 s | Elapsed : 1.00 / 2.00 s --> Total memory usage is 48780 kilobytesCompleted process "Synthesize".

Project Navigator Auto-Make Log File-------------------------------------


Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "IDE_EXT.v"Module <IDE_EXT> compiledNo errors in compilationAnalysis of file <IDE_EXT.prj> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <IDE_EXT>.Module <IDE_EXT> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <IDE_EXT>.    Related source file is IDE_EXT.v.WARNING:Xst:1305 - Output <SPCK> is never assigned. Tied to value 0.WARNING:Xst:1305 - Output <TIOA1> is never assigned. Tied to value 0.WARNING:Xst:1305 - Output <NPCS0> is never assigned. Tied to value 0.WARNING:Xst:1305 - Output <TWD> is never assigned. Tied to value 0.WARNING:Xst:1305 - Output <PCK1> is never assigned.
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