xsimtestbench_arch.cpp

采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下： 1.系统主时钟为100 MHz。 2.数据为16位-数据线上连续2次00FF后数据传输开始。 3.系统内部总线宽度为8位。

#include "work/t_f0/testbench_arch.h"
static const char * HSimCopyRightNotice = "Copyright 2004-2005, Xilinx Inc. All rights reserved.";
#include "C:/Xilinx/vhdl/hdp/std/textio/textio.h"
#include "C:/Xilinx/vhdl/hdp/ieee/std_logic_1164/std_logic_1164.h"
#include "C:/Xilinx/vhdl/hdp/ieee/std_logic_textio/std_logic_textio.h"

class _top : public HSim__s6 {
public:
    _top() : HSim__s6(false, "_top", "_top", 0, 0, HSim::VhdlDesignEntity) {}
    void archImplement(HSimConfigDecl * cfg) {
        HSim__s6 * topvh = 0;
        HSimConfigDecl * cfgvh = 0;
   topvh = new Work_t_f0_testbench_arch("t_f0");
   topvh->archImplement(cfg);
   addChild(topvh);
}
};
main(int argc, char **argv) {
  HSimDesign::initDesign();
  globalKernel->getOptions(argc,argv);
  HSim__s6 * _top_i = 0;
  try {
    StdTextio=new Std_textio("Textio");
    IeeeStd_logic_1164=new Ieee_std_logic_1164("Std_logic_1164");
    IeeeStd_logic_textio=new Ieee_std_logic_textio("Std_logic_textio");
    HSimConfigDecl cfg(" default ");
 _top_i = new _top();
  _top_i->archImplement(&cfg);
    return globalKernel->runTcl(&cfg, _top_i, "_top", argc, argv);
  }
  catch (HSimError& msg){
    try {
      globalKernel->error(msg.ErrMsg);
      return 1;
    }
    catch(...) {}
      return 1;
  }
  catch (...){
    globalKernel->fatalError();
    return 1;
  }
}