entity.cpp

来自「采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下： 1.系」· C++ 代码 · 共 63 行

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /___/   /      
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////


#include "ieee/std_logic_unsigned/std_logic_unsigned.h"
#include "ieee/std_logic_arith/std_logic_arith.h"
#include "ieee/std_logic_1164/std_logic_1164.h"
#include "work/l_eight_01/entity.h"

static const char *entFileName = "E:/大三学习资料/期末报告/DAQ_pengfu/L_eight_01.vhd";
#ifdef _MSC_VER
#pragma warning(disable: 4355)
#endif

Work_l_eight_01::Work_l_eight_01(const char *name, const char* ArchName, const char* fileName, int numOfLine): HSim__s6(false,name,"L_eight_01", ArchName, fileName, HSim::VhdlDesignEntity, numOfLine + 9)

{
  SE[0].initialize("data", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigIn);
  ;
  SE[0].setDefaultValue((char *)0);
;
  SE[1].initialize("clk", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigIn);
  ;
  SE[1].setDefaultValue((char *)0);
;
  SE[2].initialize("ce", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigIn);
  ;
  SE[2].setDefaultValue((char *)0);
;
  SE[3].initialize("rst", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigIn);
  ;
  SE[3].setDefaultValue((char *)0);
;
  SE[4].initialize("q", &IeeeStd_logic_1164->Std_logic, this, HSim::PortSigOut, HSimSA::charToMem(2));
  ;
  ;
  SetPorts();
 
}

Work_l_eight_01::~Work_l_eight_01()
{
}

void Work_l_eight_01::SetPorts()
{
}

void Work_l_eight_01::constructEntityObject()
{
;
}