f5.v

来自「verilog语言 实现5分频程序」· Verilog 代码 · 共 43 行

`timescale 1ns/10ps
module counter_n(reset,clk,clk5f);
		input reset,clk;
		output clk5f;
      wire clk5f;
		wire clk0;
		reg [2:0] counter1,counter2;
		reg clk5f1,clk5f2;
		assign clk0=~clk; 
always @(posedge clk or posedge reset)
		if (reset)
			counter1 <=0;
		else  if (counter1==3'b100)//n??????n-1
				counter1<=0;
				else
				counter1<= counter1+1;
always @(posedge clk or posedge reset)
	if(reset)
		clk5f1<=0;
	else
        //??50%????n-1?x=?n-1?/2
        //??%50????n-1?%M=?x+0.5?/(n)
		if((counter1==3'b100)||(counter1==3'b011)) 
			clk5f1<=~clk5f1;
always @(posedge clk0 or posedge reset)
		if (reset)
			counter2 <=0;
		else  if (counter2==3'b100) //n??????n-1
				counter2<=0;
				else
				counter2<= counter2+1;
always @(posedge clk0 or posedge reset)
	if(reset)
		clk5f2<=0;
	else
        //??50%????n-1?x=?n-1?/2
        //??%50????n-1?%M=?x+0.5?/(n)
		if((counter2==3'b100)||(counter2==3'b011))
			clk5f2<=~clk5f2;
			assign clk5f=clk5f1|clk5f2;
	endmodule