_primary.vhd

来自「verilog语言 实现5分频程序」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity counter_n is
    port(
        reset           : in     vl_logic;
        clk             : in     vl_logic;
        clk5f           : out    vl_logic
    );
end counter_n;