f5_tb.v

verilog语言 实现5分频程序

`timescale 1ns/10ps
module counter_n_tb  ; 
reg    reset_t   ; 
reg    clk_t   ; 
wire    clk5f_t  ; 
always #50 clk_t=~clk_t;
initial
begin
  clk_t=0; reset_t=0;
  #5 reset_t=1; #5 reset_t=0;
end  
counter_n u1(.clk(clk_t),.reset(reset_t),.clk5f(clk5f_t));
endmodule