assert_win_unchange_logic.sv

OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合、测试平台与验证

// Accellera Standard V1.0 Open Verification Library (OVL).
// Accellera Copyright (c) 2005. All rights reserved.

  parameter assert_name = "ASSERT_WIN_UNCHANGE";

  `include "std_ovl_task.h"

  `ifdef OVL_INIT_MSG
    initial
      ovl_init_msg_t; // Call the User Defined Init Message Routine
  `endif

`ifdef OVL_SHARED_CODE

  reg window = 0;

  always @ (posedge clk) begin
    if (`OVL_RESET_SIGNAL != 1'b0) begin
      if (!window && start_event == 1'b1)
        window <= 1'b1;
      else if (window && end_event == 1'b1)
        window <= 1'b0;
    end
    else begin
      window <= 1'b0;
    end
  end

`endif // OVL_SHARED_CODE

  property ASSERT_WIN_UNCHANGE_P;
  @(posedge clk)
  disable iff (`OVL_RESET_SIGNAL != 1'b1)
  (start_event && !window) |=> ( ($stable(test_expr)) [*0:$] ##1
                                 (end_event && $stable(test_expr)));
  endproperty

`ifdef OVL_ASSERT_ON

  generate

    case (property_type)
      `OVL_ASSERT : A_ASSERT_WIN_UNCHANGE_P:
                    assert property (ASSERT_WIN_UNCHANGE_P)
                    else ovl_error_t("");
      `OVL_ASSUME : M_ASSERT_WIN_UNCHANGE_P:
                    assume property (ASSERT_WIN_UNCHANGE_P);
      default     : ovl_error_t("");
    endcase

  endgenerate

`endif // OVL_ASSERT_ON

`ifdef OVL_COVER_ON

generate

 if (coverage_level != `OVL_COVER_NONE) begin

  cover_window_open:
  cover property (@(posedge clk) ( (`OVL_RESET_SIGNAL != 1'b0) &&
                                   start_event && !window) )
                 ovl_cover_t("window_open covered");

  cover_window:
  cover property (@(posedge clk) (`OVL_RESET_SIGNAL != 1'b0) throughout
                                 ((start_event && !window) ##1
                                  (!end_event && window) [*0:$] ##1
                                  (end_event && window)) )
                 ovl_cover_t("window covered");

 end

endgenerate

`endif // OVL_COVER_ON