assert_width_logic.sv

OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合、测试平台与验证

// Accellera Standard V1.0 Open Verification Library (OVL).
// Accellera Copyright (c) 2005. All rights reserved.

  parameter assert_name = "ASSERT_WIDTH";

  `include "std_ovl_task.h"

  `ifdef OVL_INIT_MSG
    initial
      ovl_init_msg_t; // Call the User Defined Init Message Routine
  `endif

  initial begin
    if ( (min_cks > 0) && (max_cks > 0) ) begin
      if (min_cks > max_cks) ovl_error_t("min_cks > max_cks");
    end
  end

  property ASSERT_WIDTH_MIN_CHECK_P;
  @(posedge clk)
  disable iff (`OVL_RESET_SIGNAL != 1'b1)
  $rose(test_expr) |-> (test_expr[*min_cks]);
  endproperty

  property ASSERT_WIDTH_MAX_CHECK_P;
  @(posedge clk)
  disable iff (`OVL_RESET_SIGNAL != 1'b1)
  $rose(test_expr) |-> (test_expr[*1:max_cks]) ##1 (!test_expr);
  endproperty

`ifdef OVL_ASSERT_ON

  generate

    case (property_type)
      `OVL_ASSERT : begin
        if (min_cks > 0) begin
          A_ASSERT_WIDTH_MIN_CHECK_P: assert property (ASSERT_WIDTH_MIN_CHECK_P)
                                      else ovl_error_t("MIN_CHECK");
        end
        if (max_cks > 0) begin
          A_ASSERT_WIDTH_MAX_CHECK_P: assert property (ASSERT_WIDTH_MAX_CHECK_P)
                                      else ovl_error_t("MAX_CHECK");
        end
      end
      `OVL_ASSUME : begin
        if (min_cks > 0) begin
          M_ASSERT_WIDTH_MIN_CHECK_P: assume property (ASSERT_WIDTH_MIN_CHECK_P);
        end
        if (max_cks > 0) begin
          M_ASSERT_WIDTH_MAX_CHECK_P: assume property (ASSERT_WIDTH_MAX_CHECK_P);
        end
      end
      default     : ovl_error_t("");
    endcase

  endgenerate

`endif // OVL_ASSERT_ON

`ifdef OVL_COVER_ON

generate

 if (coverage_level != `OVL_COVER_NONE) begin

  cover_test_expr_asserts:
  cover property (@(posedge clk) ( (`OVL_RESET_SIGNAL != 1'b0) &&
                                   $rose(test_expr)
                                 )
                 )
                 ovl_cover_t("test_expr_asserts covered");

  if (min_cks > 0) begin
    cover_test_expr_asserted_for_min_cks:
    cover property (@(posedge clk) (`OVL_RESET_SIGNAL != 1'b0) throughout 
                                   ($rose(test_expr)
                                    ##0
                                    (test_expr[*min_cks])
                                    ##1
                                    (!test_expr)
                                   )
                   )
                   ovl_cover_t("test_expr_asserted_for_min_cks covered");
  end

  if (max_cks > 0) begin
    cover_test_expr_asserted_for_max_cks:
    cover property (@(posedge clk) (`OVL_RESET_SIGNAL != 1'b0) throughout
                                   ($rose(test_expr)
                                    ##0
                                   (test_expr[*max_cks])
                                    ##1
                                   (!test_expr)
                                   )
                   )
                   ovl_cover_t("test_expr_asserted_for_max_cks covered");
  end

 end

endgenerate

`endif // OVL_COVER_ON