assert_cycle_sequence_logic.sv

OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合、测试平台与验证

// Accellera Standard V1.0 Open Verification Library (OVL).
// Accellera Copyright (c) 2005. All rights reserved.

  `include "std_ovl_task.h"

  parameter assert_name = "ASSERT_CYCLE_SEQUENCE";
  parameter NC0 = (necessary_condition == `OVL_TRIGGER_ON_MOST_PIPE);
  parameter NC1 = (necessary_condition == `OVL_TRIGGER_ON_FIRST_PIPE);
  parameter NC2 = (necessary_condition == `OVL_TRIGGER_ON_FIRST_NOPIPE);
  parameter NUM_CKS_1 = (num_cks-1);
  parameter NUM_CKS_2 = (NUM_CKS_1 > 0) ? (NUM_CKS_1 - 1) : 0; 

`ifdef OVL_INIT_MSG
  initial
    ovl_init_msg_t; // Call the User Defined Init Message Routine
`endif

  reg [num_cks-1:0]  seq_queue;

  initial begin
    if (num_cks < 2) begin
      ovl_error_t("illegal num_cks parameter");
    end
  end

  initial begin
    seq_queue = {num_cks{1'b0}};
  end

  always @ (posedge clk) begin
    if (`OVL_RESET_SIGNAL != 1'b1) begin
      seq_queue <= {num_cks{1'b0}};
    end
    else begin
      seq_queue[num_cks-1] <= NC2 ? (~(|seq_queue[num_cks-1:1])) && event_sequence[num_cks-1] :
                                    event_sequence[num_cks-1];
      seq_queue[NUM_CKS_2:0] <= (seq_queue >> 1) & event_sequence[NUM_CKS_2:0];
    end
  end

  property ASSERT_SEQUENCE_TRIGGER_ON_FIRST_P;
    @(posedge clk)
    disable iff (`OVL_RESET_SIGNAL != 1'b1)
      not (&((seq_queue[num_cks-1:1] & event_sequence[num_cks-2:0]) | ~(seq_queue[num_cks-1:1]))) != 1'b1;
  endproperty

  property ASSERT_SEQUENCE_TRIGGER_ON_MOST_P;
    @(posedge clk)
    disable iff (`OVL_RESET_SIGNAL != 1'b1)
    seq_queue[1] |-> event_sequence[0];
  endproperty

`ifdef OVL_ASSERT_ON

  generate

    case (property_type)
      `OVL_ASSERT : begin
        if (NC0) begin 
          A_ASSERT_SEQUENCE_TRIGGER_ON_MOST_P:
          assert property (ASSERT_SEQUENCE_TRIGGER_ON_MOST_P) else ovl_error_t("");
        end
        if (NC1 || NC2) begin 
          A_ASSERT_SEQUENCE_TRIGGER_ON_FIRST_P:
          assert property (ASSERT_SEQUENCE_TRIGGER_ON_FIRST_P) else ovl_error_t("");
        end
      end
      `OVL_ASSUME : begin
        if (NC0) begin 
          M_ASSERT_SEQUENCE_TRIGGER_ON_MOST_P:
          assume property (ASSERT_SEQUENCE_TRIGGER_ON_MOST_P); 
        end
        if (NC1 || NC2) begin 
          M_ASSERT_SEQUENCE_TRIGGER_ON_FIRST_P:
          assume property (ASSERT_SEQUENCE_TRIGGER_ON_FIRST_P); 
        end
      end
      default     : ovl_error_t("");
    endcase

  endgenerate

`endif // OVL_ASSERT_ON

`ifdef OVL_COVER_ON

  generate

    if (coverage_level != `OVL_COVER_NONE) begin

      cover_sequence:
      cover property (@(posedge clk) ((`OVL_RESET_SIGNAL != 1'b0) && 
                                      (((NC1 || NC2) && event_sequence[num_cks-1]) ||
                                       (NC0 && &seq_queue[num_cks-1:1]))))
                     ovl_cover_t("sequence covered");
    end

  endgenerate

`endif // OVL_COVER_ON