assert_cycle_sequence.vlib

OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合、测试平台与验证

// Accellera Standard V1.0 Open Verification Library (OVL).
// Accellera Copyright (c) 2005. All rights reserved.

`include "std_ovl_defines.h"

`module assert_cycle_sequence (clk, reset_n, event_sequence);
  parameter severity_level = `OVL_ERROR;
  parameter num_cks=2;	// number of clocks for the sequence
  parameter necessary_condition = `OVL_TRIGGER_ON_MOST_PIPE;
  parameter property_type = `OVL_ASSERT;
  parameter msg="VIOLATION";
  parameter coverage_level = `OVL_COVER_ALL;
  input clk, reset_n;
  input [num_cks-1:0] event_sequence;

`ifdef OVL_VERILOG
  `include "./vlog95/assert_cycle_sequence_logic.v"
`endif // OVL_VERILOG

`ifdef OVL_SVA
  `include "./sva31a/assert_cycle_sequence_logic.sv"
`endif // OVL_SVA

`endmodule