assert_handshake.vlib

OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合、测试平台与验证

// Accellera Standard V1.0 Open Verification Library (OVL).
// Accellera Copyright (c) 2005. All rights reserved.

`include "std_ovl_defines.h"

`module assert_handshake (clk, reset_n, req, ack);
  parameter severity_level=`OVL_ERROR;
  parameter min_ack_cycle=0;      // default don't check
  parameter max_ack_cycle=0;      // default don't check
  parameter req_drop=0;  // default don't check
  parameter deassert_count=0; // default don't check
  parameter max_ack_length=0;  // default don't check
  parameter property_type = `OVL_ASSERT;
  parameter msg="VIOLATION";
  parameter coverage_level = `OVL_COVER_ALL;
  input clk;
  input reset_n;
  input req;
  input ack;

`ifdef OVL_VERILOG
  `include "./vlog95/assert_handshake_logic.v"
`endif // OVL_VERILOG

`ifdef OVL_SVA
  `include "./sva31a/assert_handshake_logic.sv"
`endif // OVL_SVA

`endmodule