📄 lcdf_fadd.rpt
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Device-Specific Information: d:\isp\four_fadd\lcdf_fadd.rpt
lcdf_fadd
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
Cin : INPUT;
-- Node name is 'Cout'
-- Equation name is 'Cout', type is output
Cout = _LC7_C16;
-- Node name is 'D0'
-- Equation name is 'D0', type is output
D0 = _LC1_B18;
-- Node name is 'D1'
-- Equation name is 'D1', type is output
D1 = _LC8_B18;
-- Node name is 'D2'
-- Equation name is 'D2', type is output
D2 = _LC5_B18;
-- Node name is 'D3'
-- Equation name is 'D3', type is output
D3 = _LC5_B14;
-- Node name is 'D4'
-- Equation name is 'D4', type is output
D4 = _LC6_B14;
-- Node name is 'D5'
-- Equation name is 'D5', type is output
D5 = _LC2_B18;
-- Node name is 'D6'
-- Equation name is 'D6', type is output
D6 = _LC3_B18;
-- Node name is 'S0'
-- Equation name is 'S0', type is output
S0 = !_LC1_C16;
-- Node name is 'S1'
-- Equation name is 'S1', type is output
S1 = !_LC7_B14;
-- Node name is 'S2'
-- Equation name is 'S2', type is output
S2 = !_LC1_B14;
-- Node name is 'S3'
-- Equation name is 'S3', type is output
S3 = !_LC8_B14;
-- Node name is '|f_adder:u1|adder:u2|:8'
-- Equation name is '_LC8_B14', type is buried
_LC8_B14 = LCELL( _EQ001);
_EQ001 = A3 & !B3 & Cin
# !A3 & B3 & Cin
# A3 & B3 & !Cin
# !A3 & !B3 & !Cin;
-- Node name is '|f_adder:u1|or2a:u3|:4'
-- Equation name is '_LC2_B14', type is buried
!_LC2_B14 = _LC2_B14~NOT;
_LC2_B14~NOT = LCELL( _EQ002);
_EQ002 = !A3 & !B3
# !A3 & !Cin
# !B3 & !Cin;
-- Node name is '|f_adder:u2|adder:u2|:8'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = LCELL( _EQ003);
_EQ003 = A2 & B2 & !_LC2_B14
# !A2 & !B2 & !_LC2_B14
# A2 & !B2 & _LC2_B14
# !A2 & B2 & _LC2_B14;
-- Node name is '|f_adder:u2|or2a:u3|:4'
-- Equation name is '_LC4_B14', type is buried
!_LC4_B14 = _LC4_B14~NOT;
_LC4_B14~NOT = LCELL( _EQ004);
_EQ004 = !A2 & !B2
# !A2 & !_LC2_B14
# !B2 & !_LC2_B14;
-- Node name is '|f_adder:u3|adder:u2|:8'
-- Equation name is '_LC7_B14', type is buried
_LC7_B14 = LCELL( _EQ005);
_EQ005 = A1 & B1 & !_LC4_B14
# !A1 & !B1 & !_LC4_B14
# A1 & !B1 & _LC4_B14
# !A1 & B1 & _LC4_B14;
-- Node name is '|f_adder:u3|or2a:u3|:4'
-- Equation name is '_LC3_B14', type is buried
!_LC3_B14 = _LC3_B14~NOT;
_LC3_B14~NOT = LCELL( _EQ006);
_EQ006 = !A1 & !B1
# !A1 & !_LC4_B14
# !B1 & !_LC4_B14;
-- Node name is '|f_adder:u4|adder:u2|:8'
-- Equation name is '_LC1_C16', type is buried
_LC1_C16 = LCELL( _EQ007);
_EQ007 = A0 & B0 & !_LC3_B14
# !A0 & !B0 & !_LC3_B14
# A0 & !B0 & _LC3_B14
# !A0 & B0 & _LC3_B14;
-- Node name is '|f_adder:u4|or2a:u3|:4'
-- Equation name is '_LC7_C16', type is buried
_LC7_C16 = LCELL( _EQ008);
_EQ008 = A0 & _LC3_B14
# B0 & _LC3_B14
# A0 & B0;
-- Node name is ':282'
-- Equation name is '_LC3_B18', type is buried
_LC3_B18 = LCELL( _EQ009);
_EQ009 = _LC1_C16 & !_LC7_B14 & !_LC8_B14
# !_LC1_B14 & _LC1_C16
# _LC1_B14 & !_LC1_C16 & _LC7_B14
# _LC1_C16 & _LC7_B14 & _LC8_B14;
-- Node name is ':294'
-- Equation name is '_LC6_B18', type is buried
_LC6_B18 = LCELL( _EQ010);
_EQ010 = !_LC1_B14 & _LC1_C16 & !_LC7_B14 & !_LC8_B14
# _LC1_B14 & !_LC1_C16 & _LC7_B14;
-- Node name is '~315~1'
-- Equation name is '~315~1', location is LC7_B18, type is buried.
-- synthesized logic cell
_LC7_B18 = LCELL( _EQ011);
_EQ011 = _LC1_B14 & _LC1_C16 & _LC8_B14
# _LC1_C16 & _LC7_B14;
-- Node name is ':315'
-- Equation name is '_LC2_B18', type is buried
_LC2_B18 = LCELL( _EQ012);
_EQ012 = !_LC4_B18 & _LC6_B18
# _LC7_B18;
-- Node name is ':348'
-- Equation name is '_LC6_B14', type is buried
_LC6_B14 = LCELL( _EQ013);
_EQ013 = _LC1_B14 & _LC7_B14
# _LC1_C16 & !_LC7_B14
# _LC1_C16 & !_LC8_B14
# _LC1_B14 & _LC1_C16;
-- Node name is '~366~1'
-- Equation name is '~366~1', location is LC4_B18, type is buried.
-- synthesized logic cell
!_LC4_B18 = _LC4_B18~NOT;
_LC4_B18~NOT = LCELL( _EQ014);
_EQ014 = _LC7_B14
# !_LC1_C16
# !_LC1_B14 & !_LC8_B14
# _LC1_B14 & _LC8_B14;
-- Node name is ':381'
-- Equation name is '_LC5_B14', type is buried
_LC5_B14 = LCELL( _EQ015);
_EQ015 = _LC1_C16 & _LC7_B14 & _LC8_B14
# !_LC1_B14 & _LC1_C16 & _LC7_B14
# !_LC1_B14 & _LC1_C16 & _LC8_B14
# _LC1_B14 & _LC1_C16 & !_LC7_B14 & !_LC8_B14
# _LC1_B14 & !_LC1_C16 & _LC7_B14
# _LC1_B14 & _LC7_B14 & _LC8_B14;
-- Node name is ':414'
-- Equation name is '_LC5_B18', type is buried
_LC5_B18 = LCELL( _EQ016);
_EQ016 = _LC1_C16 & _LC7_B14 & _LC8_B14
# _LC1_B14 & _LC7_B14 & _LC8_B14
# !_LC1_B14 & _LC1_C16 & _LC8_B14;
-- Node name is ':447'
-- Equation name is '_LC8_B18', type is buried
_LC8_B18 = LCELL( _EQ017);
_EQ017 = _LC1_B14 & _LC1_C16 & _LC8_B14
# _LC1_C16 & !_LC7_B14 & _LC8_B14
# _LC1_B14 & _LC1_C16 & !_LC7_B14
# _LC1_B14 & !_LC1_C16 & _LC7_B14
# _LC1_B14 & _LC7_B14 & _LC8_B14;
-- Node name is ':482'
-- Equation name is '_LC1_B18', type is buried
_LC1_B18 = LCELL( _EQ018);
_EQ018 = !_LC1_B14 & _LC1_C16 & _LC7_B14
# _LC1_C16 & !_LC7_B14 & _LC8_B14
# !_LC1_B14 & _LC1_C16 & _LC8_B14
# _LC1_B14 & _LC1_C16 & !_LC7_B14
# _LC1_B14 & !_LC1_C16 & _LC7_B14;
Project Information d:\isp\four_fadd\lcdf_fadd.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,620K
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