f_fadd.rpt

这是我在ISP编程实验中独立编写的采用结构化描述的四位全加器

                           Logic cells placed in LAB 'B'
        +----------------- LC25 Cout
        | +--------------- LC24 |f_adder:u3|adder:u2|~9~1
        | | +------------- LC23 |f_adder:u4|adder:u2|~9~1
        | | | +----------- LC22 |f_adder:u4|adder:u2|~9~2
        | | | | +--------- LC21 |f_adder:u4|adder:u2|~9~3
        | | | | | +------- LC20 S0
        | | | | | | +----- LC19 S1
        | | | | | | | +--- LC18 S2
        | | | | | | | | +- LC17 S3
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC24 -> - - - - - - * - - | - * | <-- |f_adder:u3|adder:u2|~9~1
LC23 -> - - - - - * - - - | - * | <-- |f_adder:u4|adder:u2|~9~1
LC22 -> - - - - - * - - - | - * | <-- |f_adder:u4|adder:u2|~9~2
LC21 -> - - - - - * - - - | - * | <-- |f_adder:u4|adder:u2|~9~3

Pin
4    -> * - - - - * - - - | - * | <-- A0
13   -> * - - * * * * - - | - * | <-- A1
12   -> * * * * * - * * - | - * | <-- A2
11   -> * * * * * - * * * | - * | <-- A3
9    -> * - - - - * - - - | - * | <-- B0
8    -> * - * * * * * - - | - * | <-- B1
7    -> * * * * * - * * - | - * | <-- B2
6    -> * * * * * - - * * | - * | <-- B3
5    -> * * * * * - * * * | - * | <-- Cin


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                       d:\isp\four_fadd\f_fadd.rpt
f_fadd

** EQUATIONS **

A0       : INPUT;
A1       : INPUT;
A2       : INPUT;
A3       : INPUT;
B0       : INPUT;
B1       : INPUT;
B2       : INPUT;
B3       : INPUT;
Cin      : INPUT;

-- Node name is 'Cout' 
-- Equation name is 'Cout', location is LC025, type is output.
 Cout    = LCELL( _EQ001 $  VCC);
  _EQ001 = !A3 &  _X001 &  _X002 &  _X003 &  _X004
         # !B3 & !Cin &  _X001 &  _X002 &  _X004
         # !A2 & !B2 &  _X001 &  _X002
         # !A1 & !B1 &  _X002
         # !A0 & !B0;
  _X001  = EXP( A1 &  B1);
  _X002  = EXP( A0 &  B0);
  _X003  = EXP( B3 &  Cin);
  _X004  = EXP( A2 &  B2);

-- Node name is 'S0' 
-- Equation name is 'S0', location is LC020, type is output.
 S0      = LCELL( _EQ002 $  _EQ003);
  _EQ002 =  _X002 &  _X005;
  _X002  = EXP( A0 &  B0);
  _X005  = EXP(!A0 & !B0);
  _EQ003 = !_LC021 & !_LC022 & !_LC023 &  _X006;
  _X006  = EXP(!A1 & !B1);

-- Node name is 'S1' 
-- Equation name is 'S1', location is LC019, type is output.
 S1      = LCELL( _EQ004 $  _EQ005);
  _EQ004 =  _X001 &  _X006;
  _X001  = EXP( A1 &  B1);
  _X006  = EXP(!A1 & !B1);
  _EQ005 = !_LC024 &  _X007 &  _X008;
  _X007  = EXP(!A2 & !A3 & !Cin);
  _X008  = EXP(!A2 & !B2);

-- Node name is 'S2' 
-- Equation name is 'S2', location is LC018, type is output.
 S2      = LCELL( _EQ006 $  A2);
  _EQ006 = !B2 &  B3 &  Cin
         #  A3 & !B2 &  _X009
         #  B2 & !B3 &  _X010
         # !A3 &  B2 & !Cin;
  _X009  = EXP(!B3 & !Cin);
  _X010  = EXP( A3 &  Cin);

-- Node name is 'S3' 
-- Equation name is 'S3', location is LC017, type is output.
 S3      = LCELL( _EQ007 $ !Cin);
  _EQ007 =  A3 &  B3
         # !A3 & !B3;

-- Node name is '|f_adder:u3|adder:u2|~9~1' 
-- Equation name is '_LC024', type is buried 
-- synthesized logic cell 
_LC024   = LCELL( _EQ008 $  GND);
  _EQ008 = !A3 & !B2 & !B3
         # !B2 & !B3 & !Cin
         # !A3 & !B2 & !Cin
         # !A2 & !A3 & !B3
         # !A2 & !B3 & !Cin;

-- Node name is '|f_adder:u4|adder:u2|~9~1' 
-- Equation name is '_LC023', type is buried 
-- synthesized logic cell 
_LC023   = LCELL( _EQ009 $  GND);
  _EQ009 = !A3 & !B1 & !B2 & !B3
         # !B1 & !B2 & !B3 & !Cin
         # !A3 & !B1 & !B2 & !Cin
         # !A2 & !A3 & !B1 & !B3
         # !A2 & !B1 & !B3 & !Cin;

-- Node name is '|f_adder:u4|adder:u2|~9~2' 
-- Equation name is '_LC022', type is buried 
-- synthesized logic cell 
_LC022   = LCELL( _EQ010 $  GND);
  _EQ010 = !A2 & !A3 & !B1 & !Cin
         # !A1 & !A3 & !B2 & !B3
         # !A1 & !B2 & !B3 & !Cin
         # !A1 & !A3 & !B2 & !Cin
         # !A1 & !A2 & !A3 & !B3;

-- Node name is '|f_adder:u4|adder:u2|~9~3' 
-- Equation name is '_LC021', type is buried 
-- synthesized logic cell 
_LC021   = LCELL( _EQ011 $  GND);
  _EQ011 = !A1 & !A2 & !B3 & !Cin
         # !A1 & !A2 & !A3 & !Cin
         # !A2 & !B1 & !B2
         # !A1 & !A2 & !B2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                d:\isp\four_fadd\f_fadd.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,489K