sine.sim.rpt

原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成

; |sine|sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0]~59                                                                                                                            ; |sine|sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0]~59                                                                                                                            ; combout          ;
; |sine|sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]~53                                                                                                                        ; |sine|sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]~53                                                                                                                        ; combout          ;
; |sine|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3]                                                                                                                      ; |sine|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3]                                                                                                                      ; regout           ;
; |sine|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]                                                                                                                      ; |sine|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]                                                                                                                      ; regout           ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                         ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                         ; regout           ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                         ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                         ; regout           ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                         ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                         ; regout           ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[3]                                         ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[3]                                         ; regout           ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|rtl~0                                                                  ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|rtl~0                                                                  ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|process1~1                                                             ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|process1~1                                                             ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~652                                                   ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~652                                                   ; combout          ;
; |sine|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~61                                                                                                                   ; |sine|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~61                                                                                                                   ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]~653                                                ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]~653                                                ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~19                                                   ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~19                                                   ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~20                                                   ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~20                                                   ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr                                                      ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr                                                      ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~96                                                 ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~96                                                 ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~96                                                 ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~97                                                 ; cout             ;
; |sine|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0]                                                                                                                      ; |sine|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0]                                                                                                                      ; regout           ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|process0~11                                                            ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|process0~11                                                            ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~98                                                 ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~98                                                 ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~98                                                 ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~99                                                 ; cout             ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~100                                                ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~100                                                ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~100                                                ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~101                                                ; cout             ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~102                                                ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~102                                                ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~102                                                ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~103                                                ; cout             ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~104                                                ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~104                                                ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~104                                                ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~105                                                ; cout             ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]~106                                                ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]~106                                                ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~654                                                   ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~654                                                   ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~655                                                   ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~655                                                   ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~656                                                   ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~656                                                   ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~657                                                   ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~657                                                   ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~658                                                   ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~658                                                   ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~659                                                   ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~659                                                   ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~660                                                   ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~660                                                   ; combout          ;
; |sine|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]                                                                                                                                ; |sine|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]                                                                                                                                ; regout           ;
; |sine|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13                                                                                                 ; |sine|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13                                                                                                 ; combout          ;
; |sine|sld_hub:sld_hub_inst|hub_tdo~562                                                                                                                                        ; |sine|sld_hub:sld_hub_inst|hub_tdo~562                                                                                                                                        ; combout          ;
; |sine|sld_hub:sld_hub_inst|hub_tdo~563                                                                                                                                        ; |sine|sld_hub:sld_hub_inst|hub_tdo~563                                                                                                                                        ; combout          ;
; |sine|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]                                                                                                                 ; |sine|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]                                                                                                                 ; regout           ;
; |sine|sld_hub:sld_hub_inst|HUB_BYPASS_REG                                                                                                                                     ; |sine|sld_hub:sld_hub_inst|HUB_BYPASS_REG                                                                                                                                     ; regout           ;
; |sine|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|dffe1a[0]                                                                                 ; |sine|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|dffe1a[0]                                                                                 ; regout           ;
; |sine|sld_hub:sld_hub_inst|hub_tdo~564                                                                                                                                        ; |sine|sld_hub:sld_hub_inst|hub_tdo~564                                                                                                                                        ; combout          ;
; |sine|sld_hub:sld_hub_inst|hub_tdo~565                                                                                                                                        ; |sine|sld_hub:sld_hub_inst|hub_tdo~565                                                                                                                                        ; combout          ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0]          ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0]          ; regout           ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                         ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                         ; regout           ;
; |sine|sld_hub:sld_hub_inst|hub_tdo~566                                                                                                                                        ; |sine|sld_hub:sld_hub_inst|hub_tdo~566                                                                                                                                        ; combout          ;
; |sine|sld_hub:sld_hub_inst|hub_tdo~567                                                                                                                                        ; |sine|sld_hub:sld_hub_inst|hub_tdo~567                                                                                                                                        ; combout          ;
; |sine|sld_hub:sld_hub_inst|hub_tdo~568                                                                                                                                        ; |sine|sld_hub:sld_hub_inst|hub_tdo~568                                                                                                                                        ; combout          ;
; |sine|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~10                                                                                                 ; |sine|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~10                                                                                                 ; combout          ;
; |sine|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[7]                                                                                                 ; |sine|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[7]                                                                                                 ; regout           ;
; |sine|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~11                                                                                                 ; |sine|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~11                                                                                                 ; combout          ;
; |sine|sld_hub:sld_hub_inst|GEN_SHADOW_IRF~0                                                                                                                                   ; |sine|sld_hub:sld_hub_inst|GEN_SHADOW_IRF~0                                                                                                                                   ; combout          ;
; |sine|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3]                                                                                                                                ; |sine|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3]                                                                                                                                ; regout           ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]                                               ; |sine|rom1