sine.sim.rpt

原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成

; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0] ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[2] ; portadataout2    ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0] ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[3] ; portadataout3    ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0] ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[4] ; portadataout4    ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0] ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[5] ; portadataout5    ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0] ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[6] ; portadataout6    ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0] ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[7] ; portadataout7    ;
; |sine|q1[0]                                                                                                     ; |sine|q1[0]                                                                                                     ; regout           ;
; |sine|q1[1]                                                                                                     ; |sine|q1[1]                                                                                                     ; regout           ;
; |sine|q1[2]                                                                                                     ; |sine|q1[2]                                                                                                     ; regout           ;
; |sine|q1[3]                                                                                                     ; |sine|q1[3]                                                                                                     ; regout           ;
; |sine|q1[4]                                                                                                     ; |sine|q1[4]                                                                                                     ; regout           ;
; |sine|q1[0]~48                                                                                                  ; |sine|q1[0]~48                                                                                                  ; combout          ;
; |sine|q1[0]~48                                                                                                  ; |sine|q1[0]~49                                                                                                  ; cout             ;
; |sine|q1[1]~50                                                                                                  ; |sine|q1[1]~50                                                                                                  ; combout          ;
; |sine|q1[1]~50                                                                                                  ; |sine|q1[1]~51                                                                                                  ; cout             ;
; |sine|q1[2]~52                                                                                                  ; |sine|q1[2]~52                                                                                                  ; combout          ;
; |sine|q1[2]~52                                                                                                  ; |sine|q1[2]~53                                                                                                  ; cout             ;
; |sine|q1[3]~54                                                                                                  ; |sine|q1[3]~54                                                                                                  ; combout          ;
; |sine|q1[3]~54                                                                                                  ; |sine|q1[3]~55                                                                                                  ; cout             ;
; |sine|q1[4]~56                                                                                                  ; |sine|q1[4]~56                                                                                                  ; combout          ;
; |sine|q1[4]~56                                                                                                  ; |sine|q1[4]~57                                                                                                  ; cout             ;
; |sine|q1[5]~58                                                                                                  ; |sine|q1[5]~58                                                                                                  ; combout          ;
; |sine|clk                                                                                                       ; |sine|clk                                                                                                       ; combout          ;
; |sine|dout[0]                                                                                                   ; |sine|dout[0]                                                                                                   ; padio            ;
; |sine|dout[1]                                                                                                   ; |sine|dout[1]                                                                                                   ; padio            ;
; |sine|dout[2]                                                                                                   ; |sine|dout[2]                                                                                                   ; padio            ;
; |sine|dout[3]                                                                                                   ; |sine|dout[3]                                                                                                   ; padio            ;
; |sine|dout[4]                                                                                                   ; |sine|dout[4]                                                                                                   ; padio            ;
; |sine|dout[5]                                                                                                   ; |sine|dout[5]                                                                                                   ; padio            ;
; |sine|dout[6]                                                                                                   ; |sine|dout[6]                                                                                                   ; padio            ;
; |sine|dout[7]                                                                                                   ; |sine|dout[7]                                                                                                   ; padio            ;
; |sine|clk~clkctrl                                                                                               ; |sine|clk~clkctrl                                                                                               ; outclk           ;
+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                                                                                                                                                                                         ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                                                                                     ; Output Port Name                                                                                                                                                              ; Output Port Type ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0]                                                               ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[0]                                                               ; portbdataout0    ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0]                                                               ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[1]                                                               ; portbdataout1    ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0]                                                               ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[2]                                                               ; portbdataout2    ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0]                                                               ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[3]                                                               ; portbdataout3    ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0]                                                               ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[4]                                                               ; portbdataout4    ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0]                                                               ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[5]                                                               ; portbdataout5    ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0]                                                               ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[6]                                                               ; portbdataout6    ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0]                                                               ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_b[7]                                                               ; portbdataout7    ;
; |sine|altera_internal_jtag~TDO                                                                                                                                                ; |sine|altera_internal_jtag~TDO                                                                                                                                                ; tdo              ;
; |sine|altera_internal_jtag~TDO                                                                                                                                                ; |sine|altera_internal_jtag~TMSUTAP                                                                                                                                            ; tmsutap          ;
; |sine|altera_internal_jtag~TDO                                                                                                                                                ; |sine|altera_internal_jtag~TCKUTAP                                                                                                                                            ; tckutap          ;
; |sine|altera_internal_jtag~TDO                                                                                                                                                ; |sine|altera_internal_jtag                                                                                                                                                    ; tdiutap          ;
; |sine|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]                                                                                                 ; |sine|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]                                                                                                 ; regout           ;
; |sine|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]                                                                                                                      ; |sine|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]                                                                                                                      ; regout           ;
; |sine|sld_hub:sld_hub_inst|jtag_debug_mode                                                                                                                                    ; |sine|sld_hub:sld_hub_inst|jtag_debug_mode                                                                                                                                    ; regout           ;
; |sine|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]                                                                                                                             ; |sine|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]                                                                                                                             ; regout           ;