sine.sim.rpt

原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成

; Simulator Settings                                                                        ;
+-----------------------------------------------------------------+---------+---------------+
; Option                                                          ; Setting ; Default Value ;
+-----------------------------------------------------------------+---------+---------------+
; Simulation mode                                                 ; Timing  ; Timing        ;
; Start time                                                      ; 0 ns    ; 0 ns          ;
; Add pins automatically to simulation output waveforms           ; On      ; On            ;
; Check outputs                                                   ; Off     ; Off           ;
; Report simulation coverage                                      ; On      ; On            ;
; Detect setup and hold time violations                           ; Off     ; Off           ;
; Detect glitches                                                 ; Off     ; Off           ;
; Automatically save/load simulation netlist                      ; Off     ; Off           ;
; Disable timing delays in Timing Simulation                      ; Off     ; Off           ;
; Generate Signal Activity File                                   ; Off     ; Off           ;
; Group bus channels in simulation results                        ; Off     ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements ; On      ; On            ;
; Overwrite Waveform Inputs With Simulation Outputs               ; Off     ;               ;
+-----------------------------------------------------------------+---------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+---------------------------------------------------------------------------------------------------------------------+
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ALTSYNCRAM ;
+---------------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;       9.88 % ;
; Total nodes checked                                 ; 305          ;
; Total output ports checked                          ; 344          ;
; Total output ports with complete 1/0-value coverage ; 34           ;
; Total output ports with no 1/0-value coverage       ; 309          ;
; Total output ports with no 1-value coverage         ; 309          ;
; Total output ports with no 0-value coverage         ; 310          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                       ; Output Port Name                                                                                                ; Output Port Type ;
+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------+
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0] ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0] ; portadataout0    ;
; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[0] ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|q_a[1] ; portadataout1    ;