arb_fsm.v

一个用verilog编写的总线仲裁程序。多个设备共享总线

module arb_fsm(Gnt, count_reset, Req, Clk, Reset_l, count_done, gnt_done);

output [3:0]Gnt;
output count_reset;
input [3:0]Req;
input Clk;
input Reset_l;
input count_done, gnt_done;

parameter IDLE_ST=3'b000, Gnt0_ST=3'b001, Gnt1_ST=3'b010, Gnt2_ST=3'b011, Gnt3_ST=3'b100;
reg [2:0] CurrentState, NextState;

wire count_reset = (CurrentState == IDLE_ST);

always @(Reset_l or Req or count_done or CurrentState)
begin
  if(~Reset_l)
    NextState <= IDLE_ST;
  else
    case(CurrentState)
    IDLE_ST: begin
               if (Req[0])
                  NextState <= Gnt0_ST;
               else if (Req[1])
                  NextState <= Gnt1_ST;
               else if (Req[2])
                  NextState <= Gnt2_ST;
               else if (Req[3])
                  NextState <= Gnt3_ST;
               else
                  NextState <= IDLE_ST;                         
             end

    Gnt0_ST: if (count_done)
               begin                
                 if (Req[1])
                   NextState <= Gnt1_ST;
                 else if (Req[2])
                   NextState <= Gnt2_ST;
                 else if (Req[3])
                   NextState <= Gnt3_ST;
                 else if (Req[0])
                   NextState <= Gnt0_ST;
                 else
                   NextState <= IDLE_ST;
               end
             else
                NextState <= Gnt0_ST;

    Gnt1_ST: if (count_done)
               begin                
                 if (Req[2])
                   NextState <= Gnt2_ST;
                 else if (Req[3])
                   NextState <= Gnt3_ST;
                 else if (Req[0])
                   NextState <= Gnt0_ST;
                 else if (Req[1])
                   NextState <= Gnt1_ST;
                 else
                   NextState <= IDLE_ST;
               end
             else
                NextState <= Gnt1_ST;

    Gnt2_ST: if (count_done)
               begin                
                 if (Req[3])
                   NextState <= Gnt3_ST;
                 else if (Req[0])
                   NextState <= Gnt0_ST;
                 else if (Req[1])
                   NextState <= Gnt1_ST;
                 else if (Req[2])
                   NextState <= Gnt2_ST;
                 else
                   NextState <= IDLE_ST;
               end
             else
                NextState <= Gnt2_ST;
              
    Gnt3_ST: if (count_done)
               begin                
                 if (Req[0])
                   NextState <= Gnt0_ST;
                 else if (Req[1])
                   NextState <= Gnt1_ST;
                 else if (Req[2])
                   NextState <= Gnt2_ST;
                 else if (Req[3])
                   NextState <= Gnt3_ST;
                 else
                   NextState <= IDLE_ST;
               end
             else
                NextState <= Gnt3_ST;

    default:
              $display("******ERROR--Enter non-exist State!", $time);

    endcase
end

    
always @(posedge Clk or negedge Reset_l)
  begin
    if(~Reset_l)
      CurrentState <= IDLE_ST;
    else
      CurrentState <= NextState;
  end

assign Gnt[0] = gnt_done & (CurrentState == Gnt0_ST);
assign Gnt[1] = gnt_done & (CurrentState == Gnt1_ST);
assign Gnt[2] = gnt_done & (CurrentState == Gnt2_ST);
assign Gnt[3] = gnt_done & (CurrentState == Gnt3_ST);

endmodule