lcdcont.tan.qmsg

用vhdl语言实现2DPSK数字传输

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 10 -1 0 } } { "d:/program files/cad software/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/cad software/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clockdiv:div\|clockout " "Info: Detected ripple clock \"clockdiv:div\|clockout\" as buffer" {  } { { "clockdiv.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 10 -1 0 } } { "d:/program files/cad software/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/cad software/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clockdiv:div\|clockout" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lcd:mylcd\|count\[1\] register lcd:mylcd\|count\[0\] 122.7 MHz 8.15 ns Internal " "Info: Clock \"clk\" has Internal fmax of 122.7 MHz between source register \"lcd:mylcd\|count\[1\]\" and destination register \"lcd:mylcd\|count\[0\]\" (period= 8.15 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.441 ns + Longest register register " "Info: + Longest register to register delay is 7.441 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:mylcd\|count\[1\] 1 REG LC_X14_Y8_N6 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y8_N6; Fanout = 15; REG Node = 'lcd:mylcd\|count\[1\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "" { lcd:mylcd|count[1] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 34 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.511 ns) 1.517 ns lcd:mylcd\|reduce_nor~58 2 COMB LC_X14_Y8_N3 5 " "Info: 2: + IC(1.006 ns) + CELL(0.511 ns) = 1.517 ns; Loc. = LC_X14_Y8_N3; Fanout = 5; COMB Node = 'lcd:mylcd\|reduce_nor~58'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "1.517 ns" { lcd:mylcd|count[1] lcd:mylcd|reduce_nor~58 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.291 ns) + CELL(0.511 ns) 3.319 ns lcd:mylcd\|state~71 3 COMB LC_X13_Y8_N8 1 " "Info: 3: + IC(1.291 ns) + CELL(0.511 ns) = 3.319 ns; Loc. = LC_X13_Y8_N8; Fanout = 1; COMB Node = 'lcd:mylcd\|state~71'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "1.802 ns" { lcd:mylcd|reduce_nor~58 lcd:mylcd|state~71 } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.160 ns) + CELL(0.511 ns) 4.990 ns lcd:mylcd\|count\[1\]~570 4 COMB LC_X14_Y8_N2 5 " "Info: 4: + IC(1.160 ns) + CELL(0.511 ns) = 4.990 ns; Loc. = LC_X14_Y8_N2; Fanout = 5; COMB Node = 'lcd:mylcd\|count\[1\]~570'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "1.671 ns" { lcd:mylcd|state~71 lcd:mylcd|count[1]~570 } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 34 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.691 ns) + CELL(1.760 ns) 7.441 ns lcd:mylcd\|count\[0\] 5 REG LC_X14_Y8_N5 18 " "Info: 5: + IC(0.691 ns) + CELL(1.760 ns) = 7.441 ns; Loc. = LC_X14_Y8_N5; Fanout = 18; REG Node = 'lcd:mylcd\|count\[0\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "2.451 ns" { lcd:mylcd|count[1]~570 lcd:mylcd|count[0] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 34 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.293 ns 44.25 % " "Info: Total cell delay = 3.293 ns ( 44.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.148 ns 55.75 % " "Info: Total interconnect delay = 4.148 ns ( 55.75 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "7.441 ns" { lcd:mylcd|count[1] lcd:mylcd|reduce_nor~58 lcd:mylcd|state~71 lcd:mylcd|count[1]~570 lcd:mylcd|count[0] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "7.441 ns" { lcd:mylcd|count[1] lcd:mylcd|reduce_nor~58 lcd:mylcd|state~71 lcd:mylcd|count[1]~570 lcd:mylcd|count[0] } { 0.000ns 1.006ns 1.291ns 1.160ns 0.691ns } { 0.000ns 0.511ns 0.511ns 0.511ns 1.760ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.508 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.508 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "" { clk } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv:div\|clockout 2 REG LC_X11_Y7_N8 92 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X11_Y7_N8; Fanout = 92; REG Node = 'clockdiv:div\|clockout'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "3.032 ns" { clk clockdiv:div|clockout } "NODE_NAME" } "" } } { "clockdiv.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.395 ns) + CELL(0.918 ns) 8.508 ns lcd:mylcd\|count\[0\] 3 REG LC_X14_Y8_N5 18 " "Info: 3: + IC(3.395 ns) + CELL(0.918 ns) = 8.508 ns; Loc. = LC_X14_Y8_N5; Fanout = 18; REG Node = 'lcd:mylcd\|count\[0\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "4.313 ns" { clockdiv:div|clockout lcd:mylcd|count[0] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 34 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns 39.67 % " "Info: Total cell delay = 3.375 ns ( 39.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.133 ns 60.33 % " "Info: Total interconnect delay = 5.133 ns ( 60.33 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "8.508 ns" { clk clockdiv:div|clockout lcd:mylcd|count[0] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "8.508 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|count[0] } { 0.000ns 0.000ns 1.738ns 3.395ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.508 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.508 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "" { clk } "NODE_NAME" } "" } } { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clockdiv:div\|clockout 2 REG LC_X11_Y7_N8 92 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X11_Y7_N8; Fanout = 92; REG Node = 'clockdiv:div\|clockout'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "3.032 ns" { clk clockdiv:div|clockout } "NODE_NAME" } "" } } { "clockdiv.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.395 ns) + CELL(0.918 ns) 8.508 ns lcd:mylcd\|count\[1\] 3 REG LC_X14_Y8_N6 15 " "Info: 3: + IC(3.395 ns) + CELL(0.918 ns) = 8.508 ns; Loc. = LC_X14_Y8_N6; Fanout = 15; REG Node = 'lcd:mylcd\|count\[1\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "4.313 ns" { clockdiv:div|clockout lcd:mylcd|count[1] } "NODE_NAME" } "" } } { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 34 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns 39.67 % " "Info: Total cell delay = 3.375 ns ( 39.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.133 ns 60.33 % " "Info: Total interconnect delay = 5.133 ns ( 60.33 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "8.508 ns" { clk clockdiv:div|clockout lcd:mylcd|count[1] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "8.508 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|count[1] } { 0.000ns 0.000ns 1.738ns 3.395ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "8.508 ns" { clk clockdiv:div|clockout lcd:mylcd|count[0] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "8.508 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|count[0] } { 0.000ns 0.000ns 1.738ns 3.395ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "8.508 ns" { clk clockdiv:div|clockout lcd:mylcd|count[1] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "8.508 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|count[1] } { 0.000ns 0.000ns 1.738ns 3.395ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 34 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 34 -1 0 } }  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "7.441 ns" { lcd:mylcd|count[1] lcd:mylcd|reduce_nor~58 lcd:mylcd|state~71 lcd:mylcd|count[1]~570 lcd:mylcd|count[0] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "7.441 ns" { lcd:mylcd|count[1] lcd:mylcd|reduce_nor~58 lcd:mylcd|state~71 lcd:mylcd|count[1]~570 lcd:mylcd|count[0] } { 0.000ns 1.006ns 1.291ns 1.160ns 0.691ns } { 0.000ns 0.511ns 0.511ns 0.511ns 1.760ns } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "8.508 ns" { clk clockdiv:div|clockout lcd:mylcd|count[0] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "8.508 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|count[0] } { 0.000ns 0.000ns 1.738ns 3.395ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "8.508 ns" { clk clockdiv:div|clockout lcd:mylcd|count[1] } "NODE_NAME" } "" } } { "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/cad software/altera/quartus50/bin/Technology_Viewer.qrui" "8.508 ns" { clk clk~combout clockdiv:div|clockout lcd:mylcd|count[1] } { 0.000ns 0.000ns 1.738ns 3.395ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0}