lcdcont.fit.qmsg

用vhdl语言实现2DPSK数字传输

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 27 19:56:39 2007 " "Info: Processing started: Sat Oct 27 19:56:39 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off lcdcont -c lcdcont " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off lcdcont -c lcdcont" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "lcdcont EPM1270T144C5ES " "Info: Selected device EPM1270T144C5ES for design \"lcdcont\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Info: Device EPM570T144C5 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144I5 " "Info: Device EPM570T144I5 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144C5 " "Info: Device EPM1270T144C5 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144I5 " "Info: Device EPM1270T144I5 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "1 18 " "Info: No exact pin location assignment(s) for 1 pins of 18 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "ser_clk " "Info: Pin ser_clk not assigned to an exact location on the device" {  } { { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 11 -1 0 } } { "d:/program files/cad software/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/cad software/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ser_clk" } } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "" { ser_clk } "NODE_NAME" } "" } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.fld" "" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.fld" "" "" { ser_clk } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 18 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 18" {  } { { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 10 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clockdiv:div\|clockout Global clock " "Info: Automatically promoted some destinations of signal \"clockdiv:div\|clockout\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "enable_out " "Info: Destination \"enable_out\" may be non-global or may not use global clock" {  } { { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 17 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clockdiv:div\|clockout " "Info: Destination \"clockdiv:div\|clockout\" may be non-global or may not use global clock" {  } { { "clockdiv.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 10 -1 0 } }  } 0}  } { { "clockdiv.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 10 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "reset Global clock " "Info: Automatically promoted some destinations of signal \"reset\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_select " "Info: Destination \"lcd:mylcd\|lcd_select\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 17 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_data\[4\] " "Info: Destination \"lcd:mylcd\|lcd_data\[4\]\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_data\[3\] " "Info: Destination \"lcd:mylcd\|lcd_data\[3\]\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_data\[2\] " "Info: Destination \"lcd:mylcd\|lcd_data\[2\]\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_data\[1\] " "Info: Destination \"lcd:mylcd\|lcd_data\[1\]\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_data\[0\] " "Info: Destination \"lcd:mylcd\|lcd_data\[0\]\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_data\[5\] " "Info: Destination \"lcd:mylcd\|lcd_data\[5\]\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_data\[6\] " "Info: Destination \"lcd:mylcd\|lcd_data\[6\]\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd:mylcd\|lcd_data\[7\] " "Info: Destination \"lcd:mylcd\|lcd_data\[7\]\" may be non-global or may not use global clock" {  } { { "lcd.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcd.vhd" 16 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "shifter:myshift_low\|qout\[0\] " "Info: Destination \"shifter:myshift_low\|qout\[0\]\" may be non-global or may not use global clock" {  } { { "shifter.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/shifter.vhd" 9 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 12 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "reset " "Info: Pin \"reset\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "lcdcont.vhd" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.vhd" 12 -1 0 } } { "d:/program files/cad software/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/cad software/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont_cmp.qrpt" Compiler "lcdcont" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/db/lcdcont.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/" "" "" { reset } "NODE_NAME" } "" } } { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.fld" "" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/LCD/lcd_zifu/lcdcont.fld" "" "" { reset } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}