shifter.vhd

用vhdl语言实现2DPSK数字传输

-- 16位右移位寄存器;
library ieee;
use ieee.std_logic_1164.all;
entity shifter is
	port(--data	:in std_logic_vector(15 downto 0);
		reset,sr_in,clk	:in std_logic;
--		sl_in,sr_in,reset,clk:in std_logic;
--		mode	:in std_logic_vector(1 downto 0);
		qout	:buffer std_logic_vector(15 downto 0));
end shifter;

architecture behave of shifter is
--	singnal q1,q0:std_logic;
begin
	process(clk)
		begin
			if(clk'event and clk='1') then 
				if (reset='0') then
					qout<=(others=>'0');						--同步清零；
				else 
					qout<=sr_in&qout(15 downto 1);		--右移；
				end if;
			end if;
		end process;
	end behave;