clockdiv.vhd

用vhdl语言实现2DPSK数字传输

--将50MHz分频为1.966KHz；


library ieee;
use ieee.std_logic_1164.all;

entity clockdiv is
  port(
    clockin : in std_logic;
    clockout : out std_logic );
end clockdiv;

architecture behavioural of clockdiv is

signal clock_int : std_logic;
signal clock_int2: std_logic;

begin

clockout <= clock_int;

  count : process(clockin)
--  constant MAX : integer := 26666;
   constant MAX : integer := 26666;
    variable counter : integer range 0 to max;
  begin
    if rising_edge(clockin) then
      if counter = MAX then
        if clock_int = '0' then
        	clock_int <= '1';
        else
        	clock_int <= '0';
        end if;
        counter := 0;
      else
      	counter := counter + 1;
      end if;
    end if;
  end process count;

----------
-- count2 : process(clock_int)
--   constant MAX2 : integer := 200;
--   variable counter2 : integer range 0 to max2;
-- begin
--   if rising_edge(clock_int) then
--     if counter2 = MAX2 then
--     if clock_int2 = '0' then
--     	clock_int2 <= '1';
--     else
--     	clock_int2 <= '0';
--     end if;
--       counter2 := 0;
--     else
--     	counter2 := counter2 + 1;
--     end if;
--   end if;
--  end process count2;


end behavioural;

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